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TC55NEM208AFPN Datasheet(PDF) 4 Page - Toshiba Semiconductor

Part # TC55NEM208AFPN
Description  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC55NEM208AFPN Datasheet(HTML) 4 Page - Toshiba Semiconductor

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TC55NEM208AFPN/AFTN55,70
2002-09-18
4/10
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta
= −40° to 85°C, VDD = 5 V ± 10%)
READ CYCLE
TC55NEM208AFPN/AFTN
55
70
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
tRC
Read Cycle Time
55
70
tACC
Address Access Time
55
70
tCO
Chip Enable Access Time
55
70
tOE
Output Enable Access Time
30
35
tCOE
Chip Enable Low to Output Active
5
5
tOEE
Output Enable Low to Output Active
0
0
tOD
Chip Enable High to Output High-Z
25
30
tODO
Output Enable High to Output High-Z
25
30
tOH
Output Data Hold Time
10
10
ns
WRITE CYCLE
TC55NEM208AFPN/AFTN
55
70
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
tWC
Write Cycle Time
55
70
tWP
Write Pulse Width
40
50
tCW
Chip Enable to End of Write
45
55
tAS
Address Setup Time
0
0
tWR
Write Recovery Time
0
0
tODW
R/W Low to Output High-Z
25
30
tOEW
R/W High to Output Active
0
0
tDS
Data Setup Time
25
30
tDH
Data Hold Time
0
0
ns
AC TEST CONDITIONS
PARAMETER
TEST CONDITION
Output load
100 pF
+ 1 TTL Gate
Input pulse level
0.4 V, 2.4 V
Timing measurements
1.5 V
Reference level
1.5 V
tR, tF
5 ns


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