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MPC7450 Datasheet(PDF) 11 Page - Motorola, Inc |
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MPC7450 Datasheet(HTML) 11 Page - Motorola, Inc |
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11 / 52 page  MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications 11 Electrical and Thermal Characteristics Figure 2 shows the undershoot and overshoot voltage on the MPC7450. Figure 2. Overshoot/Undershoot Voltage The MPC7450 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The MPC7450 core voltage must always be provided at nominal 1.6 V (see Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OVDD or GVDD power pins. Table 3. Input Threshold Voltage Setting BVSEL Signal Processor Bus Input Threshold is Relative to: L3VSEL Signal L3 Bus Input Threshold is Relative to: Notes 0 1.8 V 0 1.8 V 1, 4 ¬HRESET Not Available ¬HRESET 1.5 V 1, 3 HRESET 2.5 V HRESET 2.5 V 1, 2 1 2.5 V 1 2.5 V 1 Notes: 1. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2. 2. To select the 2.5-V threshold option for the processor bus, BVSEL should be tied to HRESET so that the two signals change state together. Similarly, to select 2.5 V for the L3 bus, tie L3VSEL to HRESET. This is the preferred method for selecting this mode of operation. 3. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET. 4. If used, pulldown resistors should be less than 250 Ω. VIH GND GND – 0.3 V GND – 0.7 V Not to Exceed 10% OVDD/GVDD + 20% VIL OVDD/GVDD OVDD/GVDD + 5% of tSYSCLK Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com AR CH IVE D B Y F RE ES CA LE SE MI CO ND UC TO R, INC . |
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