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MPC7450 Datasheet(PDF) 6 Page - Motorola, Inc |
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MPC7450 Datasheet(HTML) 6 Page - Motorola, Inc |
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6 / 52 page  6 MPC7450 RISC Microprocessor Hardware Specifications MOTOROLA Features — Supports parity on cache and tags — Configurable core-to-L3 frequency divisors — 64-bit external L3 data bus sustains 64 bits per L3 clock cycle • Separate memory management units (MMUs) for instructions and data — 52-bit virtual address; 32- or 36-bit physical address — Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments — Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis — Separate IBATs and DBATs (four each) also defined as SPRs — Separate instruction and data translation lookaside buffers (TLBs) – Both TLBs are 128-entry, two-way set associative, and use LRU replacement algorithm – TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is performed in hardware or by system software) • Efficient data flow — Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits. — The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs — L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache. — As many as 8 outstanding, out-of-order, cache misses are allowed between the L1 data cache and L2/L3 bus. — As many as 16 out-of-order transactions can be present on the MPX bus — Store merging for multiple store misses to the same line. Only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed). — Three-entry finished store queue and five-entry completed store queue between the LSU and the L1 data cache — Separate additional queues for efficient buffering of outbound data (such as cast outs and write through stores) from the L1 data cache and L2 cache • Multiprocessing support features include the following: — Hardware-enforced, MESI cache coherency protocols for data cache — Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations • Power and thermal management — 1.6-V processor core (1.8-V processor core still supported) — The following three power-saving modes are available to the system: – Nap—Instruction fetching is halted. Only those clocks for the thermal assist unit (TAU), time base, decrementer, and JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ/QACK processor-system handshake protocol. – Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a locked and running state. All internal functional units are disabled. – Deep sleep—When the part is in the sleep state, the system can disable the PLL resulting. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com AR CH IVE D B Y F RE ES CA LE SE MI CO ND UC TO R, INC . |
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