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F280041PZS Datasheet(PDF) 7 Page - Texas Instruments |
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F280041PZS Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 217 page  7 TMS320F280049, TMS320F280049C, TMS320F280049M TMS320F280048, TMS320F280048C, TMS320F280045 TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C www.ti.com SPRS945A – JANUARY 2017 – REVISED AUGUST 2017 Submit Documentation Feedback Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280049M TMS320F280048 TMS320F280048C TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C Revision History Copyright © 2017, Texas Instruments Incorporated 2 Revision History Changes from January 25, 2017 to August 22, 2017 (from SPRS945 Revision (January 2017) to SPRS945A Revision) Page • Global: Added TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045, TMS320F280041, TMS320F280041C, TMS320F280040, and TMS320F280040C. ............................................................... 1 • Section 1.1 (Features): Updated section. ......................................................................................... 1 • Section 1.2 (Applications): Updated section. ..................................................................................... 2 • Section 1.3 (Description): Updated section. ....................................................................................... 3 • Section 1.3: Updated Device Information table ................................................................................... 3 • Figure 1-1 (Functional Block Diagram): Updated figure. ........................................................................ 5 • Section 3 (Device Comparison): Updated section. ............................................................................. 10 • Table 3-1 (Device Comparison): Updated table. Added footnote about InstaSPIN™ devices. ........................... 10 • Table 4-3 (Digital Signals): I2CA_SDA: Added "0" to GPIO column. ........................................................ 30 • Table 4-3: Added VFBSW, VSW, and X2. ...................................................................................... 30 • Section 4.4.1 (GPIO Muxed Pins): Added NOTE about unavailable GPIO pins. .......................................... 41 • Table 4-7 (Digital Signals by GPIO): Added VFBSW, VSW, and X2. ........................................................ 44 • Section 4.4.2 (Digital Inputs on ADC Pins (AIOs)): Updated section. ....................................................... 49 • Table 4-9 (Pins With Internal Pullup and Pulldown): Added "(including AIOs)" to GPIOx. ............................... 52 • Table 4-10 (Connections for Unused Pins): Updated table. .................................................................. 53 • Section 5.1 (Absolute Maximum Ratings): Updated section. ................................................................. 54 • Section 5.4 (Recommended Operating Conditions): Updated section. ..................................................... 54 • Section 5.6 (Electrical Characteristics): Updated section. ..................................................................... 54 • Section 5.5 (Power Consumption Summary): Added reference to Section 5.5.1, Operating Mode Test Description. . 56 • Section 5.5: Removed "Flash Erase/Program Currents at 100-MHz SYSCLK" table. ..................................... 56 • Table 5-1 (System Current Consumption (External Supply)): Updated table. .............................................. 56 • Table 5-2 (System Current Consumption (Internal VREG)): Updated table. ................................................ 56 • Table 5-3 (System Current Consumption (DCDC)): Updated table. .......................................................... 56 • Section 5.5.1 (Operating Mode Test Description): Added section title. Updated section. ................................. 59 • Section 5.5.2 (Current Consumption Graphs): Added section. ............................................................... 60 • Table 5-4 (Typical IDD Current Reduction per Disabled Peripheral (at 100-MHz SYSCLK)): Changed title from "Typical Current Consumption per Peripheral (at 100-MHz SYSCLK)" to "Typical IDD Current Reduction per Disabled Peripheral (at 100-MHz SYSCLK)". ................................................................................... 61 • Table 5-4: Updated table. ......................................................................................................... 61 • Section 5.8.1 (Power Management): Added NOTE about using same system voltage regulator to drive VDDIO and VDDIO_SW. ................................................................................................................... 65 • Section 5.8.1.1 (Internal 1.2-V LDO Voltage Regulator (VREG)): Updated section. ...................................... 65 • Section 5.8.1.2 (Internal 1.2-V Switching Regulator (DC-DC)): Updated section. .......................................... 65 • Section 5.8.1.3 (Power Sequencing): Added "The VREFHI voltage should not exceed VDDA at any time" to "An external power supply must be used to supply 3.3 V to VDDIO ..." paragraph. ........................................... 67 • Figure 5-6 (Reset Circuit): Updated figure. ..................................................................................... 68 • Table 5-17 (XTAL Oscillator Characteristics): Updated table. ................................................................. 73 • Table 5-20 (Internal Clock Frequencies): Changed MIN f(PLLRAWCLK) value from 120 MHz to 15 MHz. ................. 74 • Figure 5-11 (Single-ended 3.3-V External Clock): Updated figure. .......................................................... 75 • Table 5-26 (INTOSC Characteristics): Updated table. ........................................................................ 78 • Section 5.8.4 (Flash Parameters): Updated section. .......................................................................... 79 • Table 5-27 (Minimum Required Flash Wait States with Different Clock Sources and Frequencies): Updated table and footnotes. ....................................................................................................................... 79 • Table 5-28 (Flash Parameters): Changed table title from "Flash Parameters at 100 MHz" to "Flash Parameters". Updated table and footnotes. ...................................................................................................... 79 • Table 5-28: Moved data from "Flash/OTP Endurance" table and "Flash Data Retention Duration" table into "Flash Parameters" table. Removed "Flash/OTP Endurance" table and "Flash Data Retention Duration" table. ...... 79 • Figure 5-14 (Application Code With Heavy 32-Bit Floating-Point Math Instructions): Added figure. .................... 79 • Figure 5-15 (Application Code With 16-Bit If-Else Instructions): Added figure. ............................................ 79 • Section 5.8.5 (Emulation/JTAG): Updated section. ............................................................................ 81 • Figure 5-16 (Connecting to the 14-Pin JTAG Header): Updated footnote. .................................................. 82 • Figure 5-17 (Connecting to the 20-Pin JTAG Header): Updated footnote. ................................................. 82 • Table 5-29 (JTAG Timing Requirements): Updated table. .................................................................... 83 • Table 5-30 (JTAG Switching Characteristics): Updated table. ............................................................... 83 |
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