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TPS54424 Datasheet(PDF) 7 Page - Texas Instruments |
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TPS54424 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 40 page 7 TPS54424 www.ti.com SLVSDV8 – JULY 2017 Product Folder Links: TPS54424 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Characterized. Not production tested. (2) Specified by design. 6.6 Switching Characteristics TJ = -40°C to 150°C, V(VIN) = 4.5 V to 17 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN EN to start of switching 135 µs PGOOD Deglitch time PGOOD going high 272 Cycles Deglitch time PGOOD going low 16 Cycles SW ton_min Minimum on time (1) Measured at 50% to 50% of VIN, L = 1.5 µH, IOUT = 0 A 90 130 ns toff_min Minimum off time (2) V(BOOT-SW) ≥ 2.6 V 0 ns RT/CLK fsw_min Minimum switching frequency (RT mode) R(RT/CLK) = 250 kΩ 200 kHz Switching frequency (RT mode) R(RT/CLK) = 100 kΩ 450 500 550 kHz fsw_max Maximum switching frequency (RT mode) R(RT/CLK) = 30.1 kΩ 1.6 MHz fsw_clk Switching frequency synchronization range (PLL mode) 200 1600 kHz RT/CLK falling edge to SW rising edge delay (PLL mode) Measure at 500kHz with RT resistor in series with RT/CLK 70 ns HICCUP Wait time before hiccup 512 Cycles Hiccup time before restart 16384 Cycles 6.7 Timing Requirements TJ = -40°C to 150°C, V(VIN) = 4.5 V to 17 V (unless otherwise noted) MIN NOM MAX UNIT Minimum synchronization signal pulse width (PLL mode) 35 ns |
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