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NS16C2552 Datasheet(PDF) 4 Page - Texas Instruments |
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NS16C2552 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 53 page  NS16C2552, NS16C2752 SNLS238D – AUGUST 2006 – REVISED APRIL 2013 www.ti.com Signal PLCC TQFP Type Description Name Pin # Pin # TXRDY1 O 1 43 UART Transmit-ready: TXRDY2 32 28 Transmitter DMA signaling is available through this pin. When operating in the FIFO mode, the CPU selects one of two types of DMA transfer via FCR[3]. When operating in the 16450 Mode, only DMA mode 0 is allowed. Mode 0 supports single transfer DMA (and a transfer is usually made between CPU bus cycles). Mode 1 supports multi-transfer DMA where multiple transfers are made continuously until the Tx FIFO is full. Details regarding the active and inactive states of this signal are described in FIFO CONTROL REGISTER (FCR) and DMA OPERATION. INTR1 O 34 30 Interrupt Output: INTR2 17 12 INTR goes high whenever any one of the following interrupt types has an active high condition and is enabled via the IER: Receiver Error Flag; Received Data Available: time-out (FIFO Mode only); Transmitter Holding Register Empty; MODEM Status; and hardware and software flow control. The INTR signal is reset low upon the appropriate interrupt service or a Master Reset operation. SERIAL IO INTERFACE Signal PLCC TQFP Type Description Name Pin # Pin # SOUT1 O 38 35 UART Serial Data Out: SOUT2 26 22 UART transmit data output or infrared data output. The SOUT signal is set to logic 1 upon reset or idle in the UART mode when MCR[6]=0. The SOUT signal transitions to logic 0 (idle state of IrDA mode) in the infrared mode when MCR[6]=1. Note: SOUT1 and SOUT2 can not be reset to IrDA mode. SIN1 I 39 36 UART Serial Data In: SIN2 25 21 UART receive data input or infrared data input. The SIN should be idling in logic 1 in the UART mode. The SIN should be idling in logic 0 in the infrared mode. The SIN should be pulled high through a 10K resistor if not used. RTS1 O 36 33 UART Request-to-send: RTS2 23 18 When low, RTS informs the remote link partner that it is ready to receive data. The RTS output signal can be set to an active low by writing “1” to MCR[1]. The RTS output can also be configured in auto hardware flow control based on FIFO trigger level. This pin stays logic 1 upon reset or idle (i.e., between data transfers). Loop mode operation holds this signal in its inactive state. DTR1 O 37 34 UART Data-terminal-ready: DTR2 27 23 When low, DTR informs the remote link partner that the UART is ready to establish a communications link. The DTR output signal can be set to an active low by writing “1” to MCR[0]. This pin stays at logic 1 upon reset or idle. Loop mode operation holds this signal to its inactive state. CTS1 I 40 38 UART Clear-to-send: CTS2 28 24 When low, CTS indicates that the remote link partner is ready to receive data. The CTS signal is a modem status input and can be read for the appropriate channel in MSR[4]. This bit reflects the complement of the CTS signal. MSR[0] indicates whether the CTS input has changed state since the previous read of the MSR. CTS can also be configured to perform auto hardware flow control. Note: Whenever the CTS bit of the MSR changes state, an interrupt is generated if the MODEM Status Interrupt is enabled. DSR1 I 41 39 UART Data-set-ready: DSR2 29 25 When low, DSR indicates that the remote link partner is ready to establish the communications link. The DSR signal is a MODEM status input and can be read for the appropriate channel in MSR[5]. This bit reflects the complement of the DSR signal. MSR[1] indicates whether the DSR input has changed state since the previous read of the MODEM Status Register. Note: Whenever the DSR bit of the MSR changes state, an interrupt is generated if the MODEM Status Interrupt is enabled. DCD1 I 42 40 UART Data-carrier-detect: DCD2 30 26 When low, DCD indicates that the data carrier has been detected by the remote link partner. The DCD signal is a MODEM status input and can be read for the appropriate channel in MSR[7]. This bit reflects the complement of the DCD signal. MSR[3] indicates if the DCD input has changed state since the previous reading of the MODEM Status Register. DCD has no effect on the receiver. Note: Whenever the DCD bit of the MSR changes state, an interrupt is generated if the MODEM Status Interrupt is enabled. 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: NS16C2552 NS16C2752 |
Similar Part No. - NS16C2552_17 |
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Similar Description - NS16C2552_17 |
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