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AM3352BZCZA30 Datasheet(PDF) 2 Page - Texas Instruments |
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AM3352BZCZA30 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 253 page 2 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 SPRS717J – OCTOBER 2011 – REVISED APRIL 2016 www.ti.com Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Device Overview Copyright © 2011–2016, Texas Instruments Incorporated • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock) – Power • Two Nonswitchable Power Domains (Real- Time Clock [RTC], Wake-Up Logic [WAKEUP]) • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER]) • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS]) • Dynamic Voltage Frequency Scaling (DVFS) • Real-Time Clock (RTC) – Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information – Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO – Independent Power-on-Reset (RTC_PWRONRSTn) Input – Dedicated Input Pin (EXT_WAKEUP) for External Wake Events – Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification) – Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains • Peripherals – Up to Two USB 2.0 High-Speed OTG Ports With Integrated PHY – Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps) • Integrated Switch • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces • Ethernet MACs and Switch Can Operate Independent of Other Functions • IEEE 1588v2 Precision Time Protocol (PTP) – Up to Two Controller-Area Network (CAN) Ports • Supports CAN Version 2 Parts A and B – Up to Two Multichannel Audio Serial Ports (McASPs) • Transmit and Receive Clocks up to 50 MHz • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats) • FIFO Buffers for Transmit and Receive (256 Bytes) – Up to Six UARTs • All UARTs Support IrDA and CIR Modes • All UARTs Support RTS and CTS Flow Control • UART1 Supports Full Modem Control – Up to Two Master and Slave McSPI Serial Interfaces • Up to Two Chip Selects • Up to 48 MHz – Up to Three MMC, SD, SDIO Ports • 1-, 4- and 8-Bit MMC, SD, SDIO Modes • MMCSD0 has Dedicated Power Rail for 1.8 ‑V or 3.3-V Operation • Up to 48-MHz Data Transfer Rate • Supports Card Detect and Write Protect • Complies With MMC4.3, SD, SDIO 2.0 Specifications – Up to Three I2C Master and Slave Interfaces • Standard Mode (up to 100 kHz) • Fast Mode (up to 400 kHz) – Up to Four Banks of General-Purpose I/O (GPIO) Pins • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins) • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank) – Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs – Eight 32-Bit General-Purpose Timers • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks • DMTIMER4–DMTIMER7 are Pinned Out – One Watchdog Timer – SGX530 3D Graphics Engine • Tile-Based Architecture Delivering up to 20 Million Polygons per Second • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0 • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0, and OpenMax • Fine-Grained Task Switching, Load Balancing, and Power Management • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction |
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