1

PS8613A

07/15/03

1

2

3

VDD

4

GND

5

OUTA2

6

OUTB2

7

SEL1

8

OUTB1

OUT0

OUTA3

VDD

OUTB4

OUTB3

SEL2

16

15

14

13

12

11

10

9

CLKIN

OUTA1

GND

OUTA4

ProductFeatures

• Maximumratedfrequency:133MHz

• Low cycle-to-cycle jitter

• Input to output delay, less than 200ps

• Internal feedback allows outputs to be synchronized

to the clock input

• Space-saving Packages:

150-milSOIC (W)

173-milTSSOP (L)

FunctionalDescription

The PI6C2409 is a PLL based, zero-delay buffer, with the ability

to distribute nine outputs of up to 133MHz at 3.3V.

All the outputs are distributed from a single clock input CLKIN and

output OUT0 performs zero delay by connecting a feedback to PLL.

PI6C2409 has two banks of four outputs that can be controlled by

theselectioninputs,SEL1&SEL2.Italsohasapowersparingfeature:

when input SEL1 is 0 and SEL2 is 1, PLL is turned off and all

outputs are referenced from CLKIN. PI6C2409 is available in

high drive and industrial environment versions.

An internal feedback on OUT0 is used to synchronize the

outputs to the input; the relationship between loading of this signal

and the outputs determines the input-output delay.

PI6C2409 are characterized for both commercial and

industrial operation

Block Diagram

PinConfiguration

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Zero-Delay Clock Buffer

PI6C2409

16-Pin

W, L

PLL

CLKIN

SEL1

SEL2

Decode

Logic

OUTA1

OUTA2

OUTA3

OUTA4

OUTB2

OUTB3

OUTB4

OUTB1

PI6C2409(-1, -1H)

MUX

OUT0