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BH3868BFS Datasheet(PDF) 10 Page - Rohm |
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BH3868BFS Datasheet(HTML) 10 Page - Rohm |
10 / 28 page BH3868BFS Audio ICs 10/27 ! ! ! ! Control signal specification (1) Electrical specifications and timing for bus lines and I/O stages SDA SCL P tBUF tHD : STA tHD : DAT tLOW tHIGH tSU : DAT tHD : STA tSP tSU : STA Sr tSU : STO P tR tF S Fig.1 Definition of timing on the I2C BUS Table B Characteristics of the SDA and SCL bus lines for I 2C BUS devices Rise time of both SDA and SCL signals Parameter Symbol Unit Max. Min. fSCL tHD ; STA tBUF 0 kHz SCL clock fequency Fall time of both SDA and SCL signals Set-up time for STOP condition ∗ A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH min. of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Bus free time between a STOP and START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time tLOW tHIGH tSU ; STA tHD ; DAT tSU ; DAT tR tF tSU ; STO − − 4.0 250 0∗ 4.7 4.7 4.7 4.0 4.0 100 1000 300 − − − − − − − − µs µs µs µs µs µs ns µs Capacitive load for each bus line Cb − 400 pF ns ns All values referred to VIH min. and VIL max. Levels (see Table C). |
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