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P485 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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P485 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
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3 / 19 page  SSC P485 PL Transceiver IC July 1998 3 Revision 5 24000828 ADVANCE INFORMATION SSC P485 Pin Assignments Pin Mnemonic Name Description 1 4MHZ 4 MHz Clock Out 4 MHz clock output available for host microcontroller. 2 NC No Connect 3 VSSD Digital Ground Digital ground reference. 4 XIN Crystal Input Connected to external crystal to excite the IC’s internal oscillator and digital clock. 5 XOUT Crystal Output Connected to external crystal to excite the IC’s internal oscillator and digital clock. 6VDDD Digital Supply 5.0 VDC ± 10% digital supply voltage with respect to VSSD. 7 ILD Idle Line Detect Digital output, active high. Logic 1 state indicates 10 bit times of idle line, logic 0 indicates detection of carrier or non-idle line. 8 DI Driver Input Digital input. After the preamble, a low on DI (SPACE) transmits a superior2 state on SO, a high on DI (MARK) transmits a superior1 state on SO. 9 RO Receiver Output Digital output. After the preamble and assuming standard polarity: if superior1 state is detected on SI, RO will be high (MARK), if superior2 state is detected on SI, RO will be low (SPACE). 10 WL Word Length Digital input. Logic 1 (default, internal pullup) selects 10-bit frame (START, eight data bits, STOP), logic 0 selects 11-bit frame (START, nine data bits, STOP). 11 TS* Tristate Active low digital output. Enables the external output amplifier when driven high. Tri-states the external output amplifier when driven low. 12 RST* Reset Active low digital input. RST* asynchronously forces RO and ILD outputs to a high state and TS* to a low state. RST* can be asserted anytime during normal operation to force the reset state. RST* must be active (low) for 1 µsec after VDD D and VDDA stabilize and the crystal oscillator stabilizes to guarantee the internal reset state. See Figure 10. 13 VSSA Analog Ground Analog ground reference. 14 SO Signal Output Analog signal output. Tri-state enabled with internal signal. 15 C2 Capacitor 2 Connection for 680pF capacitor to ground. 16 C1 Capacitor 1 Connection for 680pF capacitor to ground. 17 SI Signal Input Analog signal input. 18 VDDA Analog Supply 5.0 VDC ± 10% analog supply voltage with respect to VSSA. 19 TP0 Test Point 0 Reserved pin for testing. 20 VSSD Digital Ground Digital ground reference. |
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