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MSC1212Y5 Datasheet(PDF) 4 Page - Burr-Brown (TI) |
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MSC1212Y5 Datasheet(HTML) 4 Page - Burr-Brown (TI) |
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4 / 69 page  MSC1212 4 SBAS278A www.ti.com ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications from TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +1.25V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted. MSC1212Yx PARAMETER CONDITION MIN TYP MAX UNITS VOLTAGE DAC OUTPUT CHARACTERISTICS(6) Output Voltage Range AGND AVDD V Output Voltage Settling Time To ±0.003% FSR, 0200 H to FD00H 8 µs Slew Rate 1V/ µs DC Output Impedance 7 Ω Short-Circuit Current All 1s Loaded to DAC Register 20 mA IDAC OUTPUT CHARACTERISTICS Full-Scale Output Current Maximum VREF = 2.5V 25 mA Maximum Short-Circuit Current Duration Indefinite Compliance Voltage AVDD – 1.5 V Relative Accuracy Over Full Range 0.185 % of FSR Zero Code Error 0.5 % of FSR Full-Scale Error –0.4 % of FSR Gain Error –0.6 % of FSR ANALOG POWER-SUPPLY REQUIREMENTS Analog Power-Supply Voltage AVDD 4.75 5.25 V Analog Current IADC + IVREF Analog OFF, PDAD = 1 < 1 nA ADC Current IADC PGA = 1, Buffer OFF 200 µA PGA = 128, Buffer OFF 500 µA PGA = 1, Buffer ON 240 µA PGA = 128, Buffer ON 850 µA VDAC Current IVDAC Excluding Load Current External Reference 250 µA VREF Supply Current IVREF ADC ON, VDAC OFF 250 µA NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD – 1.5V with buffer ON. To calibrate gain, turn buffer off. (3) ∆V OUT is change in digital result. (4) 9pF switched capacitor at fSAMP clock frequency (see Figure 6). (5) Linearity calculated using a reduced code range of 512 to 65024; output unloaded. (6) Ensured by design and characterization, not production tested. MSC1212Yx PARAMETER CONDITION MIN TYP MAX UNITS ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Buffer OFF AGND – 0.1 AVDD + 0.1 V Buffer ON AGND + 50mV AVDD – 1.5 V Full-Scale Input Voltage Range (In+) – (In–); See Figure 4 ±V REF/PGA V Differential Input Impedance Buffer OFF 7/PGA M Ω Input Current Buffer ON 0.5 nA Bandwidth Fast Settling Filter –3dB 0.469 • fDATA Sinc2 Filter –3dB 0.318 • fDATA Sinc3 Filter –3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Ranges 1 128 Input Capacitance Buffer On 9 pF Input Leakage Current Multiplexer Channel Off, T = +25 °C 0.5 pA Burnout Current Sources Sensor Input Open Circuit ±2 µA ADC OFFSET DAC Offset DAC Range ±V REF/(2 • PGA) V Offset DAC Monotonicity 8 Bits Offset DAC Gain Error ±1.5 % of Range Offset DAC Gain Error Drift 1 ppm/ °C SYSTEM PERFORMANCE Resolution 24 Bits ENOB 22 Bits Output Noise See Typical Characteristics No Missing Codes Sinc3 Filter 24 Bits Integral Nonlinearity End Point Fit, Differential Input ±0.0015 %FSR Offset Error After Calibration 7.5 ppm of FS Offset Drift(1) Before Calibration 0.02 ppm of FS/ °C Gain Error(2) After Calibration 0.005 % Gain Error Drift(1) Before Calibration 1.0 ppm/ °C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range –50 50 % of FS |
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