MPC9608

TIMING SOLUTIONS

9

The pin-to-pin skew is defined as the worst case difference in propa-

gation delay between any similar delay path within a single device.

GND

GND

GND

GND

CCLK

FB_IN

test reference

The time from the PLL controlled edge to the non controlled edge, di-

vided by the time between PLL controlled edges, expressed as a per-

centage.

GND

Figure 11. Output Duty Cycle (DC)

Figure 12. I/O Jitter

random sample of cycles.

CCLK

FB_IN

Figure 13. Cycle-to-cycle Jitter

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs.

Figure 14. Period Jitter

The deviation in cycle time of a signal with respect to the ideal period

over a random sample of cycles.

Figure 15. Output Transition Time Test Reference

2.4

0.55

GND

CCLK

CLK_STOP

GND

Freescale Semiconductor, Inc.

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