MJE13007

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7

VOLTAGE REQUIREMENTS (continued)

In the four application examples (Table 2) load lines are

shown in relation to the pulsed forward and reverse biased

SOA curves.

In circuits A and D, inductive reactance is clamped by the

diodes shown. In circuits B and C the voltage is clamped by

the output rectifiers, however, the voltage induced in the

primary leakage inductance is not clamped by these diodes

and could be large enough to destroy the device. A snubber

network or an additional clamp may be required to keep the

turn–off load line within the Reverse Bias SOA curve.

Load lines that fall within the pulsed forward biased SOA

curve during turn–on and within the reverse bias SOA curve

during turn–off are considered safe, with the following

assumptions:

1. The device thermal limitations are not exceeded.

2. The turn–on time does not exceed 10

µs

(see standard pulsed forward SOA curves in Figure 6).

3. The base drive conditions are within the specified

limits shown on the Reverse Bias SOA curve (Figure 7).

CURRENT REQUIREMENTS

An efficient switching transistor must operate at the

required current level with good fall time, high energy

handling capability and low saturation voltage. On this data

sheet, these parameters have been specified at 5.0 amperes

which represents typical design conditions for these devices.

The current drive requirements are usually dictated by the

voltage is specified at a forced gain condition which must be

duplicated or exceeded in the application to control the

saturation voltage.

SWITCHING REQUIREMENTS

In many switching applications, a major portion of the

For this reason considerable effort is usually devoted to

reducing the fall time. The recommended way to accomplish

this is to reverse bias the base–emitter junction during

turn–off. The reverse biased switching characteristics for

inductive loads are shown in Figures 12 and 13 and resistive

loads in Figures 10 and 11. Usually the inductive load

components will be the dominant factor in SWITCHMODE

applications and the inductive switching data will more

closely represent the device performance in actual

application. The inductive switching characteristics are

derived from the same circuit used to specify the reverse

biased SOA curves, (see Table 1) providing correlation

between test procedures and actual use conditions.

SWITCHING TIME NOTES

In resistive switching circuits, rise, fall, and storage times

have been defined and apply to both current and voltage

waveforms since they are in phase. However, for inductive

loads which are common to SWITCHMODE power

supplies and any coil driver, current and voltage waveforms

are not in phase. Therefore, separate measurements must be

made on each waveform to determine the total switching

time. For this reason, the following new terms have been

defined.

An enlarged portion of the turn–off waveforms is shown

in Figure 12 to aid in the visual identity of these terms. For

the designer, there is minimal switching loss during storage

time and the predominant switching power losses occur

during the crossover interval and can be obtained using the

standard equation from AN222A:

Typical inductive switching times are shown in Figure 13.

relationship may not be valid.

As is common with most switching transistors, resistive

switching is specified at 25

°C and has become a benchmark

for designers. However, for designers of high frequency

converter circuits, the user oriented specifications which

make this a “SWITCHMODE” transistor are the inductive