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M-CAS-C8237 Datasheet(PDF) 3 Page - Altera Corporation

Part No. M-CAS-C8237
Description  PROGRAMMABLE DMA CONTROLLER ALTERA CORE
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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Programming Single Mask Register Bits:
Request Register
Write Request Register Command:
Write Single Mask Register Bit Command:
A3
A2
A1
A0
IORN
IOWN
1
0
0
1
1
0
A3
A2
A1
A0
IORN
IOWN
1
0
1
0
1
0
Each channel has a request bit associated with it in the 4-bit
Request register. These are non-maskable and subject to pri-
oritization by the Priority Encoder. Each register bit is set or
reset separately under software control or is cleared upon
generation of a TC or external EOPN. The entire register is
cleared by a Reset. In order to make a software request, the
channel must be in Block Mode.
X
X
X
X
D3
D2
D1
D0
Bit0: 0 -> Clear channel 0 mask bit
1 -> Set channel 0 mask bit
Bit1: 0 -> Clear channel 1 mask bit
1 -> Set channel 1 mask bit
X
X
X
X
X
D2
D1
D0
Bit2: 0 -> Clear channel 2-mask bit
Bit1 & Bit0: 00 -> Channel 0
1 -> Set channel 2 mask bit
01 -> Channel 1
Bit3: 0 -> Clear channel 3-mask bit
10 -> Channel 2
1 -> Set channel 3 mask bit
11 -> Channel 3
Status Register
Bit2: 0 -> Reset request bit
Read Status Register Command:
1 -> Set request bit
A3
A2
A1
A0
IORN
IOWN
1
0
0
0
0
1
Mask Register
Each channel has a mask bit associated with it which can be
set to disable the incoming DREQ. Each mask bit is set when
its associated channel produces an EOPN if the channel is
not programmed for Auto initialize. Each bit of the 4-bit Mask
register may also be set or cleared separately under software
control. The entire register is also set by a Reset. This dis-
ables all DMA requests until a clear Mask register instruction
allows them to occur.
This register is available to be read out of the C8237 by the
microprocessor. It contains information about the status of the
devices at this point. Bits 0-3 are set when that channel
reaches a TC or an external EOPN is applied. These bits are
cleared upon Reset and on each Status Read. Bits 4-7 are
set whenever their corresponding channel is requesting.
D7
D6
D5
D4
D3
D2
D1
D0
Programming All Mask Register Bits:
Bit0: 1 -> Channel 0 has reached TC
Write All Mask Register Bits Command:
Bit1: 1 -> Channel 1 has reached TC
A3
A2
A1
A0
IORN
IOWN
1
1
1
1
1
0
Bit2: 1 -> Channel 2 has reached TC
Bit3: 1 -> Channel 3 has reached TC
Bit4: 1 -> Channel 0 request
X
X
X
X
X
D2
D1
D0
Bit5: 1 -> Channel 1 request
Bit1 & Bit0: 00 -> Channel 0
Bit6: 1 -> Channel 2 request
01 -> Channel 1
Bit7: 1 -> Channel 3 request
10 -> Channel 2
11 -> Channel 3
Bit2: 0 -> Clear mask bit
1 -> Set mask bit
Cast, Inc.
3




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