NCN49599

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6

Table 4. NCN49599 QFN PIN FUNCTION DESCRIPTION

Pin Number

Description

Type

I/O

Pin Name

23

VDD1V8

P

1.8 V regulator output. A decoupling capacitor of at least 1

mF is

required for stability

26

TXD

Out

D, 5VS, OD

UART transmit output

27

RXD

In

D, 5VS

UART receive input

28

SCK

Out

D, 5VS

SPI interface to external Flash: clock

29

SDI

In

D, 5VS, ST

SPI interface to external Flash: serial data input (Note 6)

30

SDO

Out

D, 5VS

SPI interface to external Flash: serial data output

31

CSB

In

D, 5VS

SPI interface to external Flash: chip select

32

IO2

In/Out

D, 5VS, ST

Must be kept low while firmware is loaded over the serial inter-

face; available as a normal GPIO afterwards (Note 3)

33

SEN

In

D, 5VS, PD, ST

Boot mode selection (refer to Boot Loader section)

34

BR1

In

D, 5VS

UART baud rate selection

35

BR0

In

D, 5VS

UART baud rate selection

37

RESB

In

D, 5VS, ST

Reset (active low)

38

TEST

In

D, 5VS, ST, PD

Production hardware test enable (Note 5)

39

TX_ENB

Out

D, 5VS, OD

Transmit enable (active low)

40

NC

This pin is not connected and must be connected to ground (recommended) or left open

41

TX_OUT

Out

A

Transmitter output

42

ALC_IN

In

A

Automatic level control input

43

VDDA

P

3.3 V analog supply

44

VSSA

P

Analog ground

45

RX_OUT

Out

A

Output of receiver operational amplifier

46

RX_IN

In

A

Non−inverting input of receiver operational amplifier

47

REF_OUT

Out

A

Internal voltage reference. A decoupling capacitor of at least 1

mF

is required for stability

48

ZC_IN

In

A

50/60 Hz input for mains zero crossing detection

49

ENB

In

D

Enable / shutdown power amplifier (active low)

50

A+

In

A

Non−inverting input of operational amplifier A

51

A−

In

A

Inverting input of operational amplifier A

52

A_OUT

Out

A

Output of operational amplifier A

53

VCC

P

Positive supply for power amplifiers A and B

54

B_OUT1

Out

A

Output of operational amplifier B

55

B_OUT2

Out

A

Output of operational amplifier B

3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general− purpose

IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation for details.

4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has

been loaded, the pin is available as a GPIO.

5. During normal operation, this pin must be tied to ground (recommended) or left open.

6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.

7. During normal operation, it is recommended that this pin is tied to ground.

8. During normal operation, this pin must be tied to Vdd.

9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.

P:

Power pin

5VS:

5 V safe; pin that supports the presence of 5 V if used as input or as open−drain output

A:

Analogue pin

Out:

Output signal

D:

Digital pin

In:

Input signal

PD:

Internal Pull Down resistor (Note 9)

OD:

Open Drain Output