NCN49597

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5

PIN DESCRIPTION − QFN Package

NCN49597

1

2

3

4

5

6

7

8

9

10

11

12

13

39

38

37

36

35

34

33

32

31

30

29

28

27

IO8

IO6

TMS

TCK

TDI

TDO

IO0

IO5

IO4

IO3

NC

ZC_IN

SDO

CSB

IO2

SEN

BR1

BR0

IO1

TEST

NC

NC

TRST

RES

TX_EN

NC

Figure 2. QFN Pin−out of NCN49597 (top view)

Table 4. NCN49597 QFN PIN FUNCTION DESCRIPTION

Pin Number

Pin Name

I/O

Type

Description

1

ZC_IN

In

A

50/60 Hz input for mains zero crossing detection

3..5, 12..14

IO3..IO7

In/Out

D, 5VS, ST

General purpose I/O’s (Note 3)

6, 33

IO0, IO1

In/Out

D, 5VS, ST

General purpose I/O’s (Notes 3 and 4)

13, 23

IO8, IO9

In/Out

D, 5VS, ST, PD

General purpose IO (Notes 3 and 9)

7

TDO

Out

D

JTAG test data output

8

TDI

In

D, 5VS, PD, ST

JTAG test data input (Note 7)

9

TCK

In

D, 5VS, PD

JTAG test clock (Note 7)

10

TMS

In

D, 5VS, PD

JTAG test mode select (Note 7)

11

TRSTB

In

D, 5VS, PD, ST

JTAG test reset (active low) (Note 8)

15

EXT_CLK_E

In

D, 5VS, PD, ST

External clock enable input

16

DATA/PRES

Out

D, 5VS, OD

Output of transmitted data (DATA) or PRE_SLOT signal (PRES)

17

XIN

In

A, 1.8 V

Crystal oscillator input

18

XOUT

Out

A, 1.8 V

Crystal oscillator output (output must be left floating when XIN is

driven by an external clock)

19

VDD1V8

P

1.8 V regulator output. A decoupling capacitor of at least 1

mF is

required for stability

20

VSS

P

Digital ground

21

VDD

P

3.3 V digital supply

3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general−pur-

pose IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation

for details.

4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has

been loaded, the pin is available as a GPIO.

5. During normal operation, this pin must be tied to ground (recommended) or left open.

6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.

7. During normal operation, it is recommended that this pin is tied to ground.

8. During normal operation, this pin must be tied to Vdd.

9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.