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RT8092DCGQW Datasheet(PDF) 3 Page - Richtek Technology Corporation |
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RT8092DCGQW Datasheet(HTML) 3 Page - Richtek Technology Corporation |
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3 / 27 page  RT8092 3 DS8092-03 January 2017 www.richtek.com © Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function WL-CSP-15B 1.2x2 WQFN-14L 3.5x3.5 A1, B1 7, 8 PVIN Power input. Input capacitor CIN must be placed as close to IC as possible. A2, B2 10, 11 LX Switch node. A3, B3, C3 -- PGND Power ground. C1 -- AGND Analog ground. C2 13 SDA I2C interface data input. D1 6 AVDD Analog and I2C interface power input. D2 2 SCL I2C interface clock input. D3 14 VSEL Nominal VOUT setting select input pin. VSEL = Low selects {0x11.ENSEL0, 0x11.VoutSEL0[6:0], 0x14.PWM0}. VSEL = High selects {0x10.ENSEL1, 0x10.VoutSEL1[6:0], 0x14.PWM1}. E1 4 VOUT Step-down converter output voltage sense input. E2 3 GNDR Remote ground sense input. E3 1 EN Enable control input. The IC enable control pin turns on the step-down converter if the internal register ENSEL bit = 1. If ENSEL = 0, EN goes high still cannot enable step-down converter. The EN pin includes a internal pull-down current about 1 A. When IC protection occurs and is latched in shutdown state, toggling EN or re-power AVDD can reset the latch state. -- 5, 9 NC No internal connection. -- 12, 15 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Pin Configuration (TOP VIEW) WL-CSP-15B 1.2x2 (BSC) AGND PGND VSEL AVDD LX SCL PVIN PGND PGND PVIN LX SDA VOUT EN GNDR C1 C2 C3 D3 D1 D2 A1 A2 A3 B3 B1 B2 E1 E2 E3 WQFN-14L 3.5x3.5 VOUT GNDR EN SCL GND LX NC LX NC PVIN 12 11 10 9 13 14 1 2 3 4 7 6 GND 15 8 5 |
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