2004 November 8

6

LPC2124

Philips Semiconductors

Single Chip 32-bit Microcontroller

Erratasheet

CAP.1

Problem when selecting P0.21 as a capture 1.3 input (timer1)

Introduction:

P0.21 and P0.19 may be configured as capture inputs via the PINSEL register.

Problem:

When PINSEL(11:10) is set to "11" P0.21 is not internally connected as capture 1.3

Work-around:

To use P0.21 as capture 1.3, PINSEL(7:6) must also be set to "11" which means that P0.19 must

be selected as capture input 1.2.

VPBDIV.1

Incorrect read of VPBDIV

Introduction:

The Peripheral Bus Divider (VPBDIV) divides the processor clock (CCLK) by one, two, or four. This

is the clock that is provided to the peripheral bus.

Problem:

Reading the VPBDIV register may return an incorrect value.

work-around:

Performing two consecutive reads of the VPBDIV assures that the correct value is returned.

Timer.1

Missed Interrupt Potential

Introduction:

The Timers may be configured so that events such as Match, Capture, and PWM, cause interrupts.

Bits in the Interrupt Register (IR) indicate the source of the interrupt, whether from Capture or

Match.

Problem:

If more than one interrupt for multiple Match events using the same Timer are enabled, it is possible

that one of the match interrupts may not be recognized. If this occurs no more interrupts from that

specific match register will be recognized. This could happen in a scenario where the match events

are very close to each other. This issue also affects the Capture functionality.

Specific details:

Suppose that two match events are very close to each other (Say Match0 and Match1). Also

assume that the Match0 event occurs first. When the Match0 interrupt occurs the 0th bit of the

Interrupt Register will be set. To exit the Interrupt Service Routine of Match0, this bit has to be

cleared in the Interrupt Register. The clearing of this bit might be done by using the following

statement:

T0_IR = 0x1;

It is possible that software will be writing a 1 to bit 0 of the Interrupt Register while a Match1 event

occurs, meaning that hardware needs to set the bit 1 of the Interrupt Register. In this case, since

hardware is accessing the register at the same time as software, bit 1 for Match1 never gets set,

causing the interrupt to be missed.

In summary, while software is writing to the Interrupt Register, any Match or Capture event (which

are configured to interrupt the core) occurring at the same time may result in the subsequent

interrupt not being recognized.

Similarly for the Capture event, if a capture event occurs while a Match event is being is serviced

then the Capture event might be missed if the software and hardware accesses coincide.