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TAS5701 Datasheet(PDF) 11 Page - Texas Instruments |
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TAS5701 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 28 page t h1 t su1 t su2 t h2 SCLK (Input) LRCLK (Input) SDIN T0026-03 t (edge) t su FORMATx, CONFIG_x, GAIN_x, RESET TAS5701 www.ti.com SLOS559A – JUNE 2008 – REVISED AUGUST 2010 SERIAL AUDIO PORTS SLAVE MODE Serial audio ports slave mode over recommended operating conditions (unless otherwise noted) TEST PARAMETER MIN TYP MAX UNIT CONDITIONS fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS CL = 30 pF 1.024 12.288 MHz tsu1 Setup time, LRCLK to SCLK rising edge 10 ns th1 Hold time, LRCLK from SCLK rising edge 10 ns tsu2 Setup time, SDIN to SCLK rising edge 10 ns th2 Hold time, SDIN from SCLK rising edge 10 ns LRCLK frequency 32 48 192 kHz SCLK duty cycle 40% 50% 60% LRCLK duty cycle 40% 50% 60% SCLK SCLK rising edges between LRCLK rising edges 32 64 edges t(edge) SCLK LRCLK clock edge with respect to the falling edge of SCLK –1/4 1/4 period Figure 2. Slave Mode Serial Data Interface Timing HARDWARE SELECT PINS over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tsu Setup time, FORMATx, CONFIG_x, GAIN_x to RESET rising edge 100 ms Figure 3. Mode Pins Setup Time Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TAS5701 |
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