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LMR23630APDRRR Datasheet(PDF) 8 Page - Texas Instruments |
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LMR23630APDRRR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 42 page  8 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Product Folder Links: LMR23630 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated (1) Ensured by design. 7.6 Timing Requirements Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT HICCUP MODE NOC (1) Number of cycles that LS current limit is tripped to enter hiccup mode 64 Cycles TOC Hiccup retry delay time SOIC package 5 ms WSON package 10 SOFT START TSS Internal soft-start time SOIC package, the time of internal reference to increase from 0 V to 1 V 2 ms WSON package, the time of internal reference to increase from 0 V to 1 V 6 ms POWER GOOD TPGOOD_RISE Power-good flag rising transition deglitch delay 150 μs TPGOOD_FALL Power-good flag falling transition deglitch delay 18 μs (1) Ensured by design. 7.7 Switching Characteristics Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) PARAMETER MIN TYP MAX UNIT SW (SW PIN) TON_MIN Minimum turnon time SOIC package 60 ns WSON package 60 90 ns TOFF_MIN (1) Minimum turnoff time 100 ns OSCILLATOR (RT and EN/SYNC PIN) fSW_DEFAULT Oscillator default frequency Fixed frequency version or RT pin open circuit 340 400 460 kHz fADJ Minimum adjustable frequency RT = 198 kΩ with 1% accuracy 150 200 250 kHz Maximum adjustable frequency RT = 17.8 kΩ with 1% accuracy 1750 2150 2425 kHz fSYNC SYNC frequency range 200 2200 kHz VSYNC Amplitude of SYNC clock AC signal (measured at SYNC pin) 2.8 5.5 V TSYNC_MIN Minimum sync clock ON-time and OFF-time 100 ns |
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