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LMK60E0-212M Datasheet(PDF) 3 Page - Texas Instruments |
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LMK60E0-212M Datasheet(HTML) 3 Page - Texas Instruments |
3 / 17 page NC OE GND 1 2 3 4 5 6 OUTN VDD OUTP 3 LMK60E2-156M, LMK60E0-156M, LMK60E0-212M www.ti.com SNAS718A – DECEMBER 2016 – REVISED JUNE 2017 Product Folder Links: LMK60E2-156M LMK60E0-156M LMK60E0-212M Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 5 Pin Configuration and Functions SIA Package 6-pin QFM Top View Pin Functions PIN I/O DESCRIPTION NAME NO. POWER GND 3 Ground Device ground VDD 6 Analog 3.3-V power supply OUTPUT BLOCK OUTP, OUTN 4, 5 Universal Differential output pair (LVPECL, LVDS or HCSL). DIGITAL CONTROL / INTERFACES NC 2 N/A No connect OE 1 LVCMOS Output enable (internal pullup). When set to low, output pair is disabled and set at high impedance. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD Device supply voltage –0.3 3.6 V VIN Output voltage for logic inputs –0.3 VDD + 0.3 V VOUT Output voltage for clock outputs –0.3 VDD + 0.3 V TJ Junction temperature 150 °C TSTG Storage temperature –40 125 °C (1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 |
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