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ICX058AK Datasheet(PDF) 2 Page - Sony Corporation |
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ICX058AK Datasheet(HTML) 2 Page - Sony Corporation |
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2 / 18 page  – 2 – ICX058AK Substrate voltage SUB – GND Supply voltage Vertical clock input voltage Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H φ1, Hφ2 – Vφ4 H φ1, Hφ2, LHφ1, RG, VGG – GND H φ1, Hφ2, LHφ1, RG, VGG – SUB VL – SUB V φ1, Vφ2, Vφ3, Vφ4, VDD, VOUT – VL RG – VL VGG, VSS, H φ1, Hφ2, LHφ1 – VL Storage temperature Operating temperature Block Diagram and Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note) Note) : Photo sensor Horizontal register Cy Ye Cy Ye Mg G Mg G Cy Ye Cy Ye GMgGMg Cy Ye Cy Ye Mg G Mg G Pin No. 1 2 3 4 5 6 7 8 V φ4 V φ3 V φ2 V φ1 GND VGG VSS VOUT Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Output amplifier gate bias Output amplifier source Signal output 9 10 11 12 13 14 15 16 VDD GND SUB VL RG LH φ1 H φ1 H φ2 Output amplifier drain supply GND Substrate (Overflow drain) Protective transistor bias Reset gate clock Horizontal register final stage transfer clock Horizontal register transfer clock Horizontal register transfer clock Symbol Description Pin No. Description Pin Description Absolute Maximum Ratings –0.3 to +55 –0.3 to +18 –55 to +10 –15 to +20 to +10 to +15 to +17 –17 to +17 –10 to +15 –55 to +10 –65 to +0.3 –0.3 to +30 –0.3 to +24 –0.3 to +20 –30 to +80 –10 to +60 V V V V V V V V V V V V V V °C °C ∗1 VDD, VOUT, VSS – GND VDD, VOUT, VSS – SUB V φ1, Vφ2, Vφ3, Vφ4 – GND V φ1, Vφ2, Vφ3, Vφ4 – SUB Item Ratings Unit Remarks ∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%. Symbol |
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