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ICS601G-01ILFT Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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ICS601G-01ILFT Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 8 page LOW PHASE NOISE CLOCK MULTIPLIER MDS 601-01 L 5 Revision 111204 In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com ICS601-01 Note 1: Switching occurs nominally at VDD/2 AC Electrical Characteristics VDD = 3.3V ±10%, Ambient Temperature -40 to +85° C Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x, maximum input frequency is 13.75 MHz). Operating Supply Current IDD No load, 125 MHz 22 30 mA Short Circuit Current Each output ±40 ±60 mA Input Capacitance CIN OE, select pins 5 pF Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency Fin 10 27 MHz Output Frequency at 3.3V or 5V 156 MHz Output Rise Time tOR 0.8 to 2.0V no load 1.5 ns Output Fall Time tOF 0.8 to 2.0V, no load 1.5 ns Output Clock Duty Cycle at VDD/2 45 50 55 % Maximum Absolute jitter, short term, 125 MHz No load ±50 ±75 ps Maximum jitter, one sigma, 125 MHz (x5) No load 12 20 ps Phase Noise, relative to carrier, 125 MHz (x5) 100 Hz offset -90 -94 dBc/Hz Phase Noise, relative to carrier, 125 MHz (x5) 1 kHz -116 -120 dBc/Hz Phase Noise, relative to carrier, 125 MHz (x5) 10 kHz offset -118 -122 dBc/Hz Phase Noise, relative to carrier, 125 MHz (x5) 100 kHz offset -115 -119 dBc/Hz Parameter Symbol Conditions Min. Typ. Max. Units |
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