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ICS950812YFLFT Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS950812YFLFT Datasheet(HTML) 3 Page - Integrated Circuit Systems |
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3 / 29 page  3 ICS950812 0542G—08/21/03 Pin Configuration (Continued) PIN # PIN NAME PIN TYPE DESCRIPTION 29 SDATA I/O Data pin for I2C circuitry 5V tolerant 30 SCLK IN Clock pin of I2C circuitry 5V tolerant 31 GND PWR Ground pin. 32 VDD3V66 PWR Power pin for the 3V66 clocks. 33 3V66_0/FS5** I/O Frequency select latch input pin / 3.3V 66.66MHz clock output. 34 PCI_STOP#* IN Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low 35 3V66_1/VCH_CLK/FS4** I/O Frequency select latch input pin / 3.3V 66.66MHz clock output / 48MHz VCH clock output. 36 GND PWR Ground pin. 37 VDD48 PWR Power pin for the 48MHz output.3.3V 38 48MHz_DOT OUT 48MHz clock output. 39 48MHz_USB/FS3** I/O Frequency select latch input pin / 3.3V 48MHz clock output. 40 FS2 IN Frequency select pin. 41 GND PWR Ground pin. 42 IREF OUT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 43 MULTSEL* IN 3.3V LVTTL input for selection the current multiplier for CPU outputs 44 CPUCLKC2 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 45 CPUCLKT2 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 46 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 47 GND PWR Ground pin. 48 CPUCLKC1 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 49 CPUCLKT1 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 50 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 51 CPUCLKC0 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 52 CPUCLKT0 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 53 CPU_STOP#* IN Stops all CPUCLK besides the free running clocks 54 FS0 IN Frequency select pin. 55 FS1 IN Frequency select pin. 56 REF OUT 14.318 MHz reference clock. |
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