AD9629-65EBZ datasheet(9/33 Pages) AD

Part #	AD9629-65EBZ

Description	12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

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Manufacturer	AD [Analog Devices]

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9 / 33 page

AD9629

Data Sheet

Rev. B | Page 8 of 32

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Min

Typ

Max

Unit

SPI TIMING REQUIREMENTS

tDS

Setup time between the data and the rising edge of SCLK

2

ns

tDH

Hold time between the data and the rising edge of SCLK

2

ns

tCLK

Period of the SCLK

40

ns

tS

Setup time between CSB and SCLK

2

ns

tH

Hold time between CSB and SCLK

2

ns

tHIGH

SCLK pulse width high

10

ns

tLOW

SCLK pulse width low

10

ns

tEN_SDIO

Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge

10

ns

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge

10

ns

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AD9629-65EBZ Datasheet(PDF) 9 Page - Analog Devices

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