ICS9248YG-192-T datasheet(2/12 Pages) ICST

Part #	ICS9248YG-192-T

Description	Frequency Timing Generator for Transmeta Systems

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Manufacturer	ICST [Integrated Circuit Systems]

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ICS9248-192

0540E—08/20/03

Pin Descriptions

Pin number

Pin name

Type

Description

1

GNDREF

Power

Ground for 14.318 MHz reference clock outputs

2

X1

Input

14.318 MHz crystal input

3

X2

Output

14.318 MHz crystal output

4PD#

Input

Asynchronous active low input pin used to power down the device

into a low power state. The internal clocks are disabled and the

VCO and the crystal are stopped. The latency of the power down

will not be greater than 3ms.

12, 11, 10, 7, 6, 5

PCICLK (5:0)

Output

3.3V PCI clock outputs, free running selectable

8

GNDPCI

Power

Ground for PCI clock outputs

9

VDDPCI

Power

3.3V power for the PCI clock outputs

Sel48_24#

Input

Selects 24MHz (0) or 48MHz (1) output

24_48MHz

Output

Selectable output either 24MHz or 48MHz

13

SDATA

I/O

Data pin for I

2C circuitry 5V tolerant

14

SCLK

IN

Clock pin of I

2C circuitry 5V tolerant

CPU3.3-2.5#

Input

3.3 (1) or 2.5 (0) VDD buffer strength selection, has pullup to VDD,

nominal 30K resistor.

48MHz

Output

3.3V 48 MHz clock output, fixed frequency clock typically used with

USB devices

17

GND48

Power

Ground for 48 MHz clocks

18

VDD48

Power

3.3V power for 48/24 MHz clocks

19

SEL 66/60#

Input

Control for the frequency of clocks at the

CPU & PCICLK output pins.

"0" = 60 MHz. "1" = 66.6 MHz.

The PCI clock is multiplexed to run at 33.3 MHz

for both selected cases.

20

VDD_Core

Power

Isolated 3.3V power for core

21

GND_Core

Power

Isolated ground for core

22

PCI_Stop#

Input

Synchronous active low input used to stop the PCICLK in active low

state. It will not effect PCICLK_F or any other outputs.

23

CPUCLK0

Output

CPU clock outputs selectable 2.5V or 3.3V.

24

GNDLCPU

Power

Ground for CPU clock outputs

25

VDDLCPU

Power

2.5V or 3.3V power for CPU clock outputs

26

CPU_STOP#

Input

Asynchronous active low input pin used to stop the CPUCLK in

active low state, all other clocks will continue to run. The CPUCLK

will have a "Turnon " latency of at least 3 CPU clocks.

27

REF

Output

3.3V 14.318 MHz reference clock output

28

VDDREF

Power

3.3V power for 14.318 MHz reference clock outputs.

15

16

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ICS9248YG-192-T Datasheet(PDF) 2 Page - Integrated Circuit Systems

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