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9FGV0841AKILF Datasheet(PDF) 8 Page - Integrated Device Technology |
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9FGV0841AKILF Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 17 page 8-OUTPUT VERY LOW-POWER PCIE GEN1-2-3-4 CLOCK GENERATOR WITH ZO=100OHMS 8 JUNE 26, 2017 9FGV0841 DATASHEET Electrical Characteristics–DIF Low Power HCSL Outputs Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Scope averaging on fast setting 1.6 2.3 3.5 V/ns 1,2,3 Scope averaging on slow setting 1.3 1.9 2.9 V/ns 1,2,3 Slew rate matching ΔTrf Slew rate matching, Scope averaging on 7 20 % 1,2,4 Voltage High VHIGH 660 784 850 7 Voltage Low VLOW -150 -33 150 7 Max Voltage Vmax 816 1150 7 Min Voltage Vmin -300 -42 7 Vswing Vswing Scope averaging off 300 1634 mV 1,2,7 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 427 550 mV 1,5,7 Crossing Voltage (var) Δ-Vcross Scope averaging off 12 140 mV 1,6,7 2 Measured from differential waveform 7 At default SMBus amplitude settings. Measurement on single ended signal using absolute value. (Scope averaging off) mV Slew rate Trf Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) mV 1Guaranteed by design and characterization, not 100% tested in production. 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions SYMBOL PARAMETER CONDITIONS MIN TYP MAX Specification Limit UNITS NOTES tjphPCIeG1-CC PCIe Gen 1 21 25 35 86 ps (p-p) 1, 2, 3 PCIe Gen 2 Low Band 10kHz < f < 1.5MHz (PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz) 0.9 0.9 1.1 3 ps (rms) 1, 2 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) (PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz) 1.5 1.6 1.9 3.1 ps (rms) 1, 2 tjphPCIeG3-CC PCIe Gen 3 (PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) 0.3 0.37 0.44 1 ps (rms) 1, 2 tjphPCIeG4-CC PCIe Gen 4 (PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) 0.3 0.37 0.44 0.5 ps (rms) 1, 2 Notes on PCIe Filtered Phase Jitter Table 1 Applies to all differential outputs, guaranteed by design and characterization. Phase Jitter, PLL Mode tjphPCIeG2-CC 2 Calculated from Intel-supplied Clock Jitter Tool, with spread on and off. 3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12. |
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