8-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

2

JUNE 26, 2017

9FGV0831 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Management Table

Power Connections

48 47 46 45 44 43 42 41 40 39 38 37

vSS_EN_tri 1

36 DIF5#

GNDXTAL 2

35 DIF5

X1_25 3

34 vOE4#

X2 4

33 DIF4#

VDDXTAL1.8 5

32 DIF4

VDDREF1.8 6

31 VDDIO

vSADR/REF1.8 7

30 VDDA1.8

GNDREF 8

29 GNDA

GNDDIG 9

28 vOE3#

SCLK_3.3 10

27 DIF3#

SDATA_3.3 11

26 DIF3

VDDDIG1.812

25vOE2#

13 14 15 16 17 18 19 20 21 22 23 24

vv prefix indicates internal 60kOhm pull-down resistor

v

prefix indicates internal 120kOhm pull-down resistor

^

prefix indicates internal 120kOhm pull-up resistor

6 x 6 mm 48-VFQFPN, 0.4mm pitch

9FGV0831

SADR

Address

0

1101000

1

1101010

State of SADR on first application

of CKPWRGD_PD#

+

Read/Write Bit

x

x

OEx#

True O/P

Comp. O/P

0

X

X

Low

Low

1

1

0

Running

Running

Running

1

0

1

Low

Low

Low

REF

CKPWRGD_PD#

SMBus

OE bit

DIFx

1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when

CKPWRG_PD# is low, REF is Low.

Pin Number

VDD

VDDIO

GND

5

2

XTAL OSC

68

REF Power

12

9

Digital (dirty)

Power

20,38

13,21,31,39,

47

22,29,40

DIF outputs

30

29

PLL Analog

Description