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9FGV0431AKILFT Datasheet(PDF) 3 Page - Integrated Device Technology |
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9FGV0431AKILFT Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 16 page 9FGV0431 4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 3 9FGV0431 JUNE 22, 2017 Pin Descriptions Pin# Pin Name Type Pin Description 1 GNDXTAL GND GND for XTAL 2 XIN/CLKIN_25 IN Crystal input or Reference Clock input. Nominally 25MHz. 3 X2 OUT Crystal output. 4 VDDXTAL1.8 PWR Power supply for XTAL, nominal 1.8V 5 VDDREF1.8 PWR VDD for REF output. nominal 1.8V. 6 vSADR/REF1.8 LATCHED I/O Latch to select SMBus Address/1.8V LVCMOS copy of X1 pin. 7 GNDREF GND Ground pin for the REF outputs. 8 GNDDIG GND Ground pin for digital circuitry 9 VDDDIG1.8 PWR 1.8V digital power (dirty power) 10 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. 11 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant. 12 vOE0# IN Active low input for enabling DIF pair 0. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 13 DIF0 OUT Differential true clock output 14 DIF0# OUT Differential Complementary clock output 15 GND GND Ground pin. 16 VDDO1.8 PWR Power supply for outputs, nominally 1.8V. 17 vOE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 18 DIF1 OUT Differential true clock output 19 DIF1# OUT Differential Complementary clock output 20 GNDA GND Ground pin for the PLL core. 21 VDDA1.8 PWR 1.8V power for the PLL core. 22 DIF2 OUT Differential true clock output 23 DIF2# OUT Differential Complementary clock output 24 vOE2# IN Active low input for enabling DIF pair 2. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 VDDO1.8 PWR Power supply for outputs, nominally 1.8V. 26 GND GND Ground pin. 27 DIF3 OUT Differential true clock output 28 DIF3# OUT Differential Complementary clock output 29 vOE3# IN Active low input for enabling DIF pair 3. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 30 GND GND Ground pin. 31 ^CKPWRGD_PD# IN Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. 32 vSS_EN_tri LATCHED IN Latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, M = -0.25%, 0 = Spread Off |
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