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WM8215 Datasheet(PDF) 10 Page - Cirrus Logic |
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WM8215 Datasheet(HTML) 10 Page - Cirrus Logic |
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10 / 31 page  WM8215 Production Data w PD, Rev 4.3, September 2012 10 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 1-channel mode pixel period tPR1 22.2 ns Output propagation delay tPD 5 10 ns Output latency. From 1 st rising edge of MCLK after VSMP falling to data output LAT 7 MCLK periods Notes: 1. Parameters are measured at 50% of the rising/falling edge. 2. In 1-channel mode, if tMFVSF is less than 9.5ns, the output amplitude of the WM8215 will decrease. SERIAL INTERFACE Figure 4 Serial Interface Timing Test Conditions AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 45MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SCK period tSPER 83.3 ns SCK high tSCKH 37.5 ns SCK low tSCKL 37.5 ns SDI set-up time tSSU 6 ns SDI hold time tSH 6 ns SCK Rising to SEN Rising tSCRSER 37.5 ns SCK Falling to SEN Falling tSCFSEF 12 ns SEN to SCK set-up time tSEC 12 ns SEN pulse width tSEW 60 ns SEN low to SDO = Register data tSERD 30 ns SCK low to SDO = Register data tSCRD 30 ns SCK low to SDO = ADC data tSCRDZ 30 ns Note: 1. Parameters are measured at 50% of the rising/falling edge |
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