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HT98R068-1 Datasheet(PDF) 68 Page - Holtek Semiconductor Inc |
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HT98R068-1 Datasheet(HTML) 68 Page - Holtek Semiconductor Inc |
68 / 116 page Rev. 1.10 68 �e���a�� 1�� �01� Rev. 1.10 69 �e���a�� 1�� �01� HT98R068-1 Two Way Radio 8-Bit MCU HT98R068-1 Two Way Radio 8-Bit MCU In cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, INTE, must first be set. An actual external interrupt will take place when the external interrupt request flag, INTF, is set, a situation that will occur when an edge transition appears on the external INT line. The type of transition that will trigger an external interrupt, whether high to low, low to high or both is determined by the INTEG0 and INTEG1 bits, which are bits 6 and 7 respectively, in the CTRL1 control register. These two bits can also disable the external interrupt function. INTEG1 INTEG0 Edge Trigger Type 0 0 Exte�nal inte���pt disa�le 0 1 Rising edge T�igge� 1 0 �alling edge T�igge� 1 1 Both edge T�igge� The external interrupt pin is pin-shared with the I/O pin PA3 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has been set and the edge trigger type has been selected using the CTRL1 register. The pin must also be setup as an input by setting the corresponding PAC.3 bit in the port control register. When the interrupt is enabled, the stack is not full and an active transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04H, will take place. When the interrupt is serviced, the external interrupt request flag, EIF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor connections on this pin will remain valid even if the pin is used as an external interrupt input. Timer/Event Counter Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, TnE, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, TnF, is set, a situation that will occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Time Base Interrupt The internal Time base Counter interrupt is initialized by setting the Time base overflow interrupt request flag, which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call occurs. The related interrupt request flag TBF is reset, and the EMI bit is cleared to disable further mask-able interrupts. A/D Converter Interrupt The A/D Converter interrupt is initialized by setting the A/D converter request flag, caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a sub- routine call will occur. The related interrupt request flag ADF will be reset and the EMI bit cleared to disable further interrupts. |
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