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HT82A525R Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT82A525R Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
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11 / 71 page  System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from a Crystal oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Rev. 1.80 11 March 11, 2016 HT82A525R I/O Type USB 8-Bit OTP MCU with SPI T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k O S C 2 ( R C o n l y ) P C System Clocking and Pipelining F e t c h I n s t . 1 E x e c u t e I n s t . 1 F e t c h I n s t . 2 F l u s h P i p e l i n e 1 2 3 4 5 6 D E L A Y : M O V A , [ 1 2 H ] C A L L D E L A Y C P L [ 1 2 H ] : : N O P E x e c u t e I n s t . 2 F e t c h I n s t . 3 F e t c h I n s t . 6 E x e c u t e I n s t . 6 F e t c h I n s t . 7 Instruction Fetching |
Similar Part No. - HT82A525R_16 |
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Similar Description - HT82A525R_16 |
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