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UPD48576209F1 Datasheet(PDF) 46 Page - Renesas Technology Corp

Part # UPD48576209F1
Description  576M-BIT Low Latency DRAM
Download  54 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD48576209F1 Datasheet(HTML) 46 Page - Renesas Technology Corp

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µµµµPD48576209F1, µµµµPD48576218F1, µµµµPD48576236F1
R10DS0256EJ0101 Rev. 1.01
Page 46 of 53
Jan. 15, 2016
Table 3-4. Scan Register Definition (1)
Register name
Description
Instruction register
The 8 bit instruction registers hold the instructions that are executed by the TAP controller.
The register can be loaded when it is placed between the TDI and TDO pins.
The
instruction register is automatically preloaded with the IDCODE instruction at power-up
whenever the controller is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It
allows serial test data to be passed through the RAMs TAP to another device in the scan
chain with as little delay as possible. The bypass register is set LOW (VSS) when the
bypass instruction is executed.
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit
code when the controller is put in capture-DR state with the IDCODE command loaded in
the instruction register. The register is then placed between the TDI and TDO pins when
the controller is moved into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents
of the RAMs I/O ring when the controller is in capture-DR state and then is placed between
the TDI and TDO pins when the controller is moved to shift-DR state.
Several TAP
instructions can be used to activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The
second column is the name of the input or I/O at the bump and the third column is the bump
number.
Table 3-5. Scan Register Definition (2)
Register name
Bit size
Unit
Instruction register
8
bit
Bypass register
1
bit
ID register
32
bit
Boundary register
113
bit
Table 3-6. ID Register Definition
Part number
Organization
ID [31:28] vendor
revision no.
ID [27:12] part no.
ID [11:1] vendor ID no.
ID [0]
fix bit
µPD48576209F1
64M x 9
0000
0001 0001 1010 0111
00000010000
1
µPD48576218F1
32M x 18
0001
0001 0001 1010 0111
00000010000
1
µPD48576236F1
16M x 36
0010
0001 0001 1010 0111
00000010000
1


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