UPD48576118F1 datasheet(38/52 Pages) RENESAS

Part #	UPD48576118F1

Description	576M-BIT Low Latency DRAM

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Manufacturer	RENESAS [Renesas Technology Corp]

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38 / 52 page

µµµµPD48576118F1

R10DS0257EJ0101 Rev. 1.01

Page 38 of 51

Jan. 15, 2016

Table 2-8. Address and Command Setup and Hold Derating Values

Command/

t

AS/tCS VREF to

t

AS/tCS VIH(AC)

t

AH/tCH

t

AH/tCH

Unit

Address Slew

CK/CK#

MIN to CK/CK#

CK/CK#

Rate (V/ns)

Crossing

Crossing to

VREF

VIH(DC) MIN

CK, CK# Differential Slew Rate: 2.0 V/ns

2.0

0

-100

0

-50

ps

1.9

5

-100

3

-50

ps

1.8

11

-100

6

-50

ps

1.7

18

-100

9

-50

ps

1.6

25

-100

13

-50

ps

1.5

33

-100

17

-50

ps

1.4

43

-100

22

-50

ps

1.3

54

-100

27

-50

ps

1.2

67

-100

34

-50

ps

1.1

82

-100

41

-50

ps

1.0

100

-100

50

-50

ps

CK, CK# Differential Slew Rate: 1.5 V/ns

2.0

30

-70

30

-20

ps

1.9

35

-70

33

-20

ps

1.8

41

-70

36

-20

ps

1.7

48

-70

39

-20

ps

1.6

55

-70

43

-20

ps

1.5

63

-70

47

-20

ps

1.4

73

-70

52

-20

ps

1.3

84

-70

57

-20

ps

1.2

97

-70

64

-20

ps

1.1

112

-70

71

-20

ps

1.0

130

-70

80

-20

ps

CK, CK# Differential Slew Rate: 1.0 V/ns

2.0

60

-40

60

10

ps

1.9

65

-40

63

10

ps

1.8

71

-40

66

10

ps

1.7

78

-40

69

10

ps

1.6

85

-40

73

10

ps

1.5

93

-40

77

10

ps

1.4

103

-40

82

10

ps

1.3

114

-40

87

10

ps

1.2

127

-40

94

10

ps

1.1

142

-40

101

10

ps

1.0

160

-40

110

10

ps

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