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UPD48288209AF1 Datasheet(PDF) 22 Page - Renesas Technology Corp

Part # UPD48288209AF1
Description  288M-BIT Low Latency DRAM
Download  54 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD48288209AF1 Datasheet(HTML) 22 Page - Renesas Technology Corp

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µµµµPD48288209AF1, µµµµPD48288218AF1, µµµµPD48288236AF1
R10DS0254EJ0101 Rev. 1.01
Page 22 of 53
Jan. 15, 2016
Figure 2-5. Mode Register Bit Map
Notes
1.
Bits A10–A17 must be set to all ‘0’. A18-An are “Don’t Care”.
2.
BL=8 is not available for configuration 1 and 4.
3.
±30% temperature variation.
4.
Within 15%.
2.9
Read & Write configuration (Non Multiplexed Address Mode)
Table 2-4
shows, for different operating frequencies, the different
µPD48288209/18/36AF1 configurations that can be
programmed into the mode register. The READ and WRITE latency (tRL and tWL) values along with the row cycle times
(tRC) are shown in clock cycles as well as in nanoseconds.
Table 2-4. Configuration Table
Parameter
Configuration
Unit
1
Note1
2
3
4
Note1, 2
5
tRC
4
6
8
3
5
tCK
tRL
4
6
8
3
5
tCK
tWL
5
7
9
4
6
tCK
Valid frequency range
266-175
400-175
533-175
200-175
333-175
MHz
Notes 1. BL= 8 is not available.
2.
The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank.
In this instance the minimum tRC is 4 cycles.
A2
A4
A5
A17-A10
A3
A1
A0
A6
A7
A3
0
1
BL
4
A4
0
1
8 Note 2
0
0
1
1
Reserved
Note 1
A9
A7
0
1
A8
A2
A1
A0
10
Configuration
Configuration
Configuration
1 Note 2 (default)
5
Reserved
Reserved
1 Note 2
Not valid
2 (default)
PLL enabled
PLL Reset
PLL Reset
Burst Length
Burst Length
PLL Reset
Address
Mux
Address Mux
PLL reset (default)
2
3
4
10
11
01
01
00
00
1
1
0
0
1
0
1
0
11
Impedance
Matching
Impedance
Matching
A8
0
1
Resistor
External
Internal 50 Ω Note 3
(default)
A5
0
1
Nonmultiplexed
(default)
Address multiplexed
Address Mux
A9
0
1
Enabled
Termination
On-Die
Termination
Disabled (default)
On-Die
Termination
Unused
Note 2
Note 4


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