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PLQP0064KB-C Datasheet(PDF) 8 Page - Renesas Technology Corp |
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PLQP0064KB-C Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 116 page R01DS0273EJ0100 Rev.1.00 Page 8 of 116 Oct 30, 2015 RX130 Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a block diagram. Figure 1.2 Block Diagram Clock generation circuit RX CPU RAM ROM Port 1 Port 2 Port 4 Port 5 8-bit D/A converter × 2 channels CRC DOC E2 DataFlash RTCc RIICa × 1 channel 12-bit A/D converter × 17 channels TMR × 2 channels (unit 1) ELC DTCa ICUb CAC IWDTa Port A Port B Port C Port D MTU2a × 6 channels SCIh × 1 channel Port 3 Temperature sensor Port E Port H Port J Comparator B POE2a TMR × 2 channels (unit 0) SCIg × 3 channels CMT × 2 channels (unit 0) RSPIa × 1 channel Port 0 CTSUa LPT ICUb: Interrupt controller DTCa: Data transfer controller IWDTa: Independent watchdog timer ELC: Event link controller CRC: CRC (cyclic redundancy check) calculator SCIg/SCIh: Serial communications interface RSPIa: Serial peripheral interface RIICa: I2C bus interface MTU2a: Multi-function timer pulse unit 2 POE2a: Port output enable 2 CMT: Compare match timer RTCc: Realtime clock DOC: Data operation circuit CAC: Clock frequency accuracy measurement circuit CTSUa: Capacitive touch sensing unit TMR: 8-bit timer LPT: Low power timer |
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