S124 datasheet(49/98 Pages) RENESAS

Part #	S124

Description	32-bit ARM Cortex-M0 microcontroller

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Manufacturer	RENESAS [Renesas Technology Corp]

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49 / 98 page

R01DS0264EU0100 Rev.1.00

Page 49 of 95

Feb 23, 2016

S124

2. Electrical Characteristics

2.3.6

I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing

Note 1. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.

Figure 2.28

I/O ports input timing

Figure 2.29

POEG input trigger timing

Figure 2.30

GPT input capture timing

Table 2.30

I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing

Item

Symbol Min

Max

Unit

Test

conditions

I/O Ports

Input data pulse width

tPRW

1.5

-

tPcyc

Figure 2.28

POEG

POEG input trigger pulse width

tPOEW

3

-

tPcyc

Figure 2.29

GPT

Input capture pulse width

Single edge

tGTICW

1.5

-

tPDcyc

Figure 2.30

Dual edge

2.5

-

AGT

AGTIO, AGTEE input cycle

2.7 V ≤ VCC ≤ 5.5 V

tACYC*1 250

-

ns

Figure 2.31

2.4 V ≤ VCC < 2.7 V

500

-

ns

1.8 V ≤ VCC < 2.4 V

1000

-

ns

1.6 V ≤ VCC < 1.8 V

2000

-

ns

AGTIO, AGTEE input high level

width, low-level width

2.7 V ≤ VCC ≤ 5.5 V

tACKWH,

tACKWL

100

-

ns

2.4 V ≤ VCC < 2.7 V

200

-

ns

1.8 V ≤ VCC < 2.4 V

400

-

ns

1.6 V ≤ VCC < 1.8 V

800

-

ns

AGTIO, AGTO, AGTOA, AGTOB

output frequency

2.7 V ≤ VCC ≤ 5.5 V

tACYC2

62.5

-

ns

Figure 2.31

2.4 V ≤ VCC < 2.7 V

125

-

ns

1.8 V ≤ VCC < 2.4 V

250

-

ns

1.6 V ≤ VCC < 1.8 V

500

-

ns

ADC14

14-bit A/D converter trigger input pulse width

tTRGW

1.5

-

tPcyc

Figure 2.32

KINT

Key interrupt input low-level width

tKR

250

-

ns

Figure 2.33

Port

tPRW

POEG input trigger

tPOEW

Input capture

tGTICW

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