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R5F52316ADFP Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # R5F52316ADFP
Description  54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F52316ADFP Datasheet(HTML) 3 Page - Renesas Technology Corp

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R01DS0261EJ0110 Rev.1.10
Page 3 of 177
Oct 30, 2015
RX230 Group, RX231 Group
1. Overview
Low power
consumption
Low power consumption
functions
 Module stop function
 Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
 Low power timer that operates during the software standby state
Function for lower operating
power consumption
 Operating power control modes
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt
Interrupt controller (ICUb)
 Interrupt vectors: 167
 External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
 Non-maskable interrupts: 7 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, WDT interrupt, IWDT interrupt, and VBATT power monitoring
interrupt)
 16 levels specifiable for the order of priority
External bus extension
 The external address space can be divided into four areas (CS0 to CS3), each with independent
control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8-bit or 16-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
 Wait control
 Write buffer facility
DMA
DMA controller (DMACA)
 4 channels
 Three transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
Data transfer controller
(DTCa)
 Transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Interrupts
 Chain transfer function
I/O ports
General I/O ports
100-pin /64-pin /48-pin
I/O: 79/43/30 (RX231 Group), 83/47/34 (RX230 Group)
 Input: 1/1/1
Pull-up resistors: 79/43/30(RX231 Group), 83/47/34 (RX230 Group)
 Open-drain outputs: 58/34/26
 5-V tolerance: 5/3/3
Event link controller (ELC)
 Event signals of 61 types can be directly connected to the module
 Operations of timer modules are selectable at event input
 Capable of event link operation for port B and port E
Multi-function pin controller (MPC)
Capable of selecting the input/output function from multiple pins
Timers
16-bit timer pulse unit
(TPUa)
 (16 bits × 6 channels) × 1 unit
 Maximum of 16 pulse-input/output possible
 Select from among seven or eight counter-input clock signals for each channel
 Supports the input capture/output compare function
 Output of PWM waveforms in up to 15 phases in PWM mode
 Support for buffered operation, phase-counting mode (two-phase encoder input) and cascade
connected operation (32 bits × 2 channels) depending on the channel.
 Capable of generating conversion start triggers for the A/D converters
 Signals from the input capture pins are input via a digital filter
 Clock frequency measuring method
Multi-function timer pulse
unit 2 (MTU2a)
 (16 bits × 6 channels) × 1 unit
 Up to 16 pulse-input/output lines and three pulse-input lines are available based on the six 16-bit
timer channels
 Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
 Input capture function
 21 output compare/input capture registers
 Pulse output mode
 Complementary PWM output mode
 Reset synchronous PWM mode
 Phase-counting mode
 Capable of generating conversion start triggers for the A/D converter
Port output enable 2
(POE2a)
Controls the high-impedance state of the MTU’s waveform output pins
Compare match timer
(CMT)
 (16 bits × 2 channels) × 2 units
 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Watchdog timer (WDTA)
 14 bits x 1 channel
 Select from among six counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512, PCLK/
2048, PCLK/8192)
Table 1.1
Outline of Specifications (2/4)
Classification
Module/Function
Description


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