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R7FS5D97E3A01CFP Datasheet(PDF) 6 Page - Renesas Technology Corp |
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R7FS5D97E3A01CFP Datasheet(HTML) 6 Page - Renesas Technology Corp |
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6 / 115 page  R01DS0303EU0100 Rev.1.00 Page 6 of 115 Nov 3, 2016 S5D9 1. Overview Resets 14 resets: RES pin reset Power-on reset Voltage monitor reset 0 Voltage monitor reset 1 Voltage monitor reset 2 Independent Watchdog Timer reset Watchdog Timer reset Deep Software Standby reset SRAM parity error reset SRAM ECC error reset Bus master MPU error reset Bus slave MPU error reset Stack pointer error reset Software reset. See section 6, Resets in User's Manual. Low Voltage Detection (LVD) The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and the detection level can be selected in the software program. See section 8, Low Voltage Detection (LVD) in User's Manual. Clocks Main clock oscillator (MOSC) Sub-clock oscillator (SOSC) High-speed on-chip oscillator (HOCO) Middle-speed on-chip oscillator (MOCO) Low-speed on-chip oscillator (LOCO) PLL frequency synthesizer Independent Watchdog Timer (WDT) on-chip oscillator Clock out support. See section 9, Clock Generation Circuit in User's Manual. Clock Frequency Accuracy Measurement Circuit (CAC) The CAC checks the system clock frequency with a reference clock signal by counting the number of pulses of the system clock to be measured. The reference clock can be provided externally through a CACREF pin or internally from various on-chip oscillators. Event signals can be generated when the clock does not match or measurement ends. This feature is particularly useful in implementing a fail-safe mechanism for home and industrial automation applications. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User's Manual. Interrupt Controller Unit (ICU) The ICU controls which event signals are linked to the NVIC/DTC module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt Controller Unit (ICU) in User's Manual. Key interrupt function (KINT) A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function (KINT) in User's Manual. Low-power modes Power consumption can be reduced in multiple ways, including by setting clock dividers, controlling EBCLK output, controlling SDCLK output, stopping modules, selecting power control mode in normal operation, and transitioning to low-power modes. See section 11, Low- Power Modes in User's Manual. Battery backup function A battery backup function is provided for partial powering by a battery. The battery-powered area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See section 12, Battery Backup Function in User's Manual. Register write protection The register write protection function protects important registers from being overwritten because of software errors. See section 13, Register Write Protection in User's Manual. Memory Protection Unit (MPU) Four MPUs and a CPU stack pointer monitor function are provided for memory protection. See section 16, Memory Protection Unit (MPU) in User's Manual. Watchdog Timer (WDT) The WDT is a 14-bit down-counter. It can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A refresh-permitted period can be set to refresh the counter and be used as the condition for detecting when the system runs out of control. See section 27, Watchdog Timer (WDT) in User's Manual. Table 1.3 System (2 of 3) Feature Functional description |
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