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RX230 Datasheet(PDF) 66 Page - Renesas Technology Corp |
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RX230 Datasheet(HTML) 66 Page - Renesas Technology Corp |
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66 / 177 page  R01DS0261EJ0110 Rev.1.10 Page 66 of 177 Oct 30, 2015 RX230 Group, RX231 Group 4. I/O Registers 0008 C02Eh PORTE Port Output Data Register PODR 8 8 2 or 3 PCLKB 2 ICLK 0008 C031h PORTH Port Output Data Register PODR 8 8 2 or 3 PCLKB 2 ICLK 0008 C032h PORTJ Port Output Data Register PODR 8 8 2 or 3 PCLKB 2 ICLK 0008 C040h PORT0 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C041h PORT1 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C042h PORT2 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C043h PORT3 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C044h PORT4 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C045h PORT5 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C04Ah PORTA Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C04Bh PORTB Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C04Ch PORTC Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C04Dh PORTD Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C04Eh PORTE Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C051h PORTH Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C052h PORTJ Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 3 ICLK cycles when reading, 2 ICLK cycles when writing 0008 C060h PORT0 Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C061h PORT1 Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C062h PORT2 Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C063h PORT3 Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C064h PORT4 Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C065h PORT5 Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C06Ah PORTA Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C06Bh PORTB Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C06Ch PORTC Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C06Dh PORTD Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C06Eh PORTE Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C071h PORTH Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C072h PORTJ Port Mode Register PMR 8 8 2 or 3 PCLKB 2 ICLK 0008 C082h PORT1 Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB 2 ICLK Table 4.1 List of I/O Registers (Address Order) (24 / 42) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access Cycles ICLK PCLK ICLK <PCLK |
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