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R5F56519BDFP Datasheet(PDF) 5 Page - Renesas Technology Corp |
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R5F56519BDFP Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 190 page RX65N Group, RX651 Group 1. Overview R01DS0276EJ0100 Rev.1.00 Page 5 of 190 Aug 24, 2016 Timers Multifunction timer pulse unit (MTU3a) 9 channels (16 bits × 8 channels, 32 bits × 1 channel) Maximum of 28 pulse-input/output and 3 pulse-input possible Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/ 2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A) 14 of the signals are available for channel 0, 11 are available for channels 1, 3, 4, 6 to 8, 12 are available for channel 2, and 10 are available for channel 5. Input capture function 39 output compare/input capture registers Counter clear operation (synchronous clearing by compare match/input capture) Simultaneous writing to multiple timer counters (TCNT) Simultaneous register input/output by synchronous counter operation Buffered operation Support for cascade-connected operation 43 interrupt sources Automatic transfer of register data Pulse output mode Toggle/PWM/complementary PWM/reset-synchronized PWM Complementary PWM output mode Outputs non-overlapping waveforms for controlling 3-phase inverters Automatic specification of dead times PWM duty cycle: Selectable as any value from 0% to 100% Delay can be applied to requests for A/D conversion. Non-generation of interrupt requests at peak or trough values of counters can be selected. Double buffer configuration Reset synchronous PWM mode Three phases of positive and negative PWM waveforms can be output with desired duty cycles. Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2) Counter functionality for dead-time compensation Generation of triggers for A/D converter conversion A/D converter start triggers can be skipped Digital filter function for signals on the input capture and external counter clock pins PPG output trigger can be generated Event linking by the ELC Port output enable 3 (POE3a) Control of the high-impedance state of the MTU3 waveform output pins 5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11# Initiation on detection of short-circuited outputs (detection of simultaneous PWM output to the active level) Initiation by oscillation-stoppage detection or software Additional programming of output control target pins is enabled Programmable pulse generator (PPG) (4 bits × 4 groups) × 2 units Pulse output with the MTU or TPU output as a trigger Maximum of 32 pulse-output possible 8-bit timers (TMRb) (8 bits × 2 channels) × 2 units Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8, PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal Capable of output of pulse trains with desired duty cycles or of PWM signals The 2 channels of each unit can be cascaded to create a 16-bit timer Generation of triggers for A/D converter conversion Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12 Event linking by the ELC Compare match timer (CMT) (16 bits × 2 channels) × 2 units Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Event linking by the ELC Compare match timer W (CMTW) (32 bits × 1 channel) × 2 units Compare-match, input-capture input, and output-comparison output are available. Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Interrupt requests can be output in response to compare-match, input-capture, and output-comparison events. Event linking by the ELC Table 1.1 Outline of Specifications (4/8) Classification Module/Function Description |
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