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PLQP0112JA-A Datasheet(PDF) 4 Page - Renesas Technology Corp |
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PLQP0112JA-A Datasheet(HTML) 4 Page - Renesas Technology Corp |
4 / 186 page R01DS0087EJ0220 Rev.2.20 Page 4 of 186 Mar 31, 2016 RX63T Group 1. Overview I/O ports General I/O ports 144-pin LQFP I/O pins: 81 Input pins: 29 Open-drain outputs: 27 120-pin LQFP I/O pins: 72 Input pin: 21 Open-drain outputs: 26 112-pin LQFP I/O pins: 69 Input pins: 21 Open-drain outputs: 20 100-pin LQFP I/O pins: 57 Input pins: 21 Open-drain outputs: 16 64-pin LQFP I/O pins: 39 Input pins: 9 Open-drain outputs: 10 5-V tolerance: 39 48-pin LQFP I/O pins: 25 Input pins: 7 Open-drain outputs: 8 5-V tolerance: 25 Timers Multi-function timer pulse unit 3 (MTU3) (16 bits × 8 channels) Maximum of 16 pulse-input/output and 3 pulse-input possible Select eight clocks from among ten count clocks (PCLKA/1, PCLKA/4, PCLKA/16, PCLKA/64, PCLKA/256, PCLKA/1024, MTCLKA, MTCLKB, MTCLKC, and MTCLKD) for each channel (seven clocks for channel 1, four clocks for channel 5, and six clocks for channel 6 or 7) 24 output compare/input capture registers Counter-clearing operation (simultaneous clearing on compare match or input capture) Simultaneous writing to multiple timer counters (TCNT) Simultaneous input and output to registers in synchronization with counter operations Buffer operation specifiable Capable of cascade-connected operation Interrupts: 38 sources Automatic transfer of register data Pulse output modes Topple, PWM, complementary PWM, and reset-synchronous PWM modes Complementary PWM output mode Outputs non-overlapping waveforms for controlling 3-phase inverters Automatic specification of dead times PWM duty cycle: Selectable as any value from 0% to 100% Delay can be applied to requests for A/D conversion. Non-generation of interrupt requests at peak or trough values of counters can be selected. Double buffering Reset-synchronous PWM mode Three PWM waveforms and corresponding inverse waveforms are output with the desired duty cycles. Phase-counting mode Counter functionality for dead-time compensation Generation of triggers for A/D converters Differential timing for initiation of A/D conversion Port output enable 3 (POE3) Control of the high-impedance state of the MTU3 and GPT’s waveform output pins Six pins for input from signal sources: POE0, POE4, POE8, POE10, POE11, and POE12 Initiation on detection of short-circuited outputs (detection of PWM outputs having simultaneously become an active level.) Initiation by comparator-detection, oscillation-stoppage detection, or software Software control of the states of pins for output control can also be added. Table 1.1 Outline of Specifications (3/7) Classification Module/Function Description |
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