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W682310 Datasheet(PDF) 7 Page - Winbond |
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W682310 Datasheet(HTML) 7 Page - Winbond |
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7 / 35 page  W682510/W682310 6. PIN DESCRIPTION Pin Name Pin # SSOP PDIP Pin # SOP Functionality (CH1 = Channel 1, CH2 = Channel 2) VREF 1 1 This pin is used to bypass the signal ground. It needs to be decoupled to VSS through a 0.1 µF ceramic decoupling capacitor. No external loads should be tied to this pin. RO2 2 2 CH2 Non-Inverting output of the receive smoothing filter. This pin can typically drive a 600 Ω load (W682510) or 1200 Ω load (W682310). RO1 3 4 CH1 Non-Inverting output of the receive smoothing filter. This pin can typically drive a 600 Ω load (W682510) or 1200 Ω load (W682310).. PUI 4 5 Power up input signal. When this pin is HIGH (tied to VDD) the part is powered up. When LOW (tied to VSS) the part is powered down. PCMMS 5 6 PCM mode select input (serial or parallel data interface) HIGH = Parallel, LOW = Serial VDD 6 8 Power supply. This pin should be decoupled to VSS with a 0.1 µF ceramic capacitor. VSSD 7 9 This is the digital supply ground. This pin should be connected to 0V. FSR 8 10 8 kHz Frame Sync input for the PCM receive section. It can also be connected to the FST pin when transmit and receive are synchronous operations. PCMR2 9 11 CH2 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLK pins. PCMR1 10 12 CH1 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLK pins. PCMT1 11 13 CH1 PCM output data transmit pin. The output data is synchronous with the FST and BCLK pins. PCMT2 12 14 CH2 PCM output data transmit pin. The output data is synchronous with the FST and BCLK pins. FST 13 15 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes. BCLK 14 16 PCM transmit and receive bit clock input pin for CH1 and CH2 transmit. VSSA 15 18 This is the analog supply ground. This pin should be connected to 0V. μ/A-Law 16 19 Compander mode select pin. µ-Law companding is selected when this pin is LOW (tied to VSS.) A-Law companding is selected when pin is HIGH (tied to VDD.) AI1 17 21 CH1 Non-Inverting input of the first gain stage in the transmit path. AO1- 18 22 CH1 Inverting analog output of the first gain stage in the transmit path. AO2- 19 23 CH2 Inverting analog output of the first gain stage in the transmit path AI2 20 24 CH2 Non-Inverting input of the first gain stage in the transmit path. Publication Release Date: May 2003 - 7 - Revision 0.35 |
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