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PLQP0052JA-B Datasheet(PDF) 8 Page - Renesas Technology Corp |
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PLQP0052JA-B Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 98 page R01DS0248EJ0110 Rev.1.10 Page 8 of 98 Jan 13, 2016 RX23T Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a block diagram. Figure 1.2 Block Diagram 12-bit A/D converter × 10 channels MTU3c × 6ch CMT × 2 channels (unit 0) POE3b TMR × 2 channels (unit 0) TMR × 2 channels (unit 1) CMT × 2 channels (unit 1) RIICa × 1ch RSPIa × 1ch SCIg × 2ch CRC IWDTa Clock generation circuit RX CPU RAM ROM DOC DTCa ICUb CAC Comparator C × 3 channels MPU Port D Port E Port A Port B Port 9 Port 7 Port 0 Port 1 Port 3 Port 4 Port 2 ICUb: Interrupt controller DTCa: Data transfer controller IWDTa: Independent watchdog timer CRC: CRC (cyclic redundancy check) calculator SCIg: Serial communications interface RSPIa: Serial peripheral interface RIICa I2C bus interface MTU3c Multi-function timer pulse unit 3 POE3b Port output enable 3 CMT Compare match timer DOC Data operation circuit CAC Clock frequency accuracy measurement circuit MPU Memory protection unit TMR 8-bit timer |
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