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TSEV83102G0BGL Datasheet(PDF) 6 Page - ATMEL Corporation

Part # TSEV83102G0BGL
Description  10-bit 2 Gsps ADC
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

TSEV83102G0BGL Datasheet(HTML) 6 Page - ATMEL Corporation

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6
TS83102G0B
2101D–BDC–06/04
Notes:
1. Differential output buffers impedance = 100
Ω differential (50 Ω single-ended). See Figure 46 starting on page 42.
2. Histogram testing at Fs = 1 Gsps, Fin = 100 MHz, DNLrms is a component of quantization noise.
3. Histogram testing at Fs = 50 Msps, Fin = 25 MHz
4. This range of gain can be set to "1" by using the gain adjust function.
Digital Outputs (1)
Logic compatibility (depending on V
PLUSD value)
Differential ECL (V
PLUSD = -0.8V typical)
Output levels
50
Ω transmission lines, 100 Ω (2 x 50 Ω)
differentially terminated
- logic low
- logic high
- swing (each single-ended output)
- common mode
1
1
1
4
VOL
V
OH
VOH - VOL
-0.98
200
-.095
-1.17
-0.94
230
-1.05
-1.10
300
-1.15
V
V
mV
V
Logic compatibility (depending on VPLUSD value)
LVDS (VPLUSD = 1.45V typical)
Output levels 50
Ω transmission lines, 100 Ω
(2 x 50
Ω) differentially terminated
- logic low
- logic high
- swing (each single-ended output)
- common mode
max V
PLUSD = 1.525V
typ VPLUSD = 1.45V
min V
PLUSD = 1.375V
4
4
4
4
4
4
VOL
V
OH
VOH - VOL
825
200
1190
1125
1090
1310
230
1200
1575
300
1275
1210
mV
mV
mV
mV
mV
mV
DC Accuracy
DNLrms (2)
4
DNLrms
0.50
0.53
0.55
LSB
Differential non-linearity (3)
1
DNL+
1.5
2
LSB
Integral non-linearity (3)
1INL-
- 4.0
- 2.4
LSB
Integral non-linearity (3)
1INL+
2.4
4.0
LSB
Gain central value (4)
1
0.89
0.94
1.1
Gain error drift
4
23
35
ppm/°C
Input offset voltage
1
- 10
10
mV
Electrical Operating Characteristics (Continued)
V
CC = 5V ; VPLUSD = 0V (unless otherwise specified). ADC performances are independent of VPLUSD common mode
voltage and performances are guaranteed within the limits of the specified V
PLUSD range (from -0.9V to 1.7V);
V
EE = DVEE = -5V; VIN - VINB = 500 mVpp (full-scale single-ended or differential input);
clock inputs differential driven; analog-input single-ended driven.
Parameter
Test
Level
Symbol
Min
Typ
Max
Unit


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