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R5F11CCCG Datasheet(PDF) 2 Page - Renesas Technology Corp |
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R5F11CCCG Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 111 page  RL78/I1E 1. OUTLINE R01DS0274EJ0110 Rev. 1.10 Page 2 of 108 Jun 30, 2016 24-bit ∆Σ A/D converter with programmable gain instrumentation amplifier 24-bit second-order ∆Σ A/D converter (AVDD = 2.7 to 5.5 V) SNDR: 85 dB (TYP.) Output data rate: 488 sps to 15.625 ksps in normal mode 61 sps to 1.953 ksps in low power mode Programmable gain instrumentation amplifier input: 3 or 4 channels (differential input mode or single-ended input mode can be specified for each input channel) DAC for offset adjustment Variable gain: x1 to x64 On-chip temperature sensor 10-bit A/D converter 8-bit/10-bit successive approximation A/D converter (AVDD = 2.7 to 5.5 V) Analog input: 8 or 10 channels, sensor power supply (SBIAS), and internal reference voltage Internal reference voltage (1.45 V) Configurable amplifier Matrix configuration that consists of 3 operational amplifier channels and a configurable switch (AVDD = 2.7 to 5.5 V) Can be used as a 2- or 3-channel general operational amplifier Operational amplifier output: 3 channels General-purpose Analog I/O ports: 5 or 6 channels Offset voltage calibration D/A converter 12-bit R-2R resistor ladder type D/A converter (AVDD = 2.7 to 5.5 V) Analog output: 1 channel (via configurable amplifier) I/O port CMOS I/O: 10 to 14 (N-ch open drain I/O [withstanding voltage of VDD]: 6, CMOS I/O: 7 to 11, CMOS input: 3) Can be set to TTL input buffer and on-chip pull-up resistor Different potential interface: Can connect to a 2.5/3 V device On-chip clock output/buzzer output controller Others On-chip BCD (binary-coded decimal) correction circuit ROM, RAM capacities Flash ROM Data flash RAM RL78/I1E 32 pins 36 pins 32 KB 4 KB 8 KB R5F11CBC R5F11CCC |
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