S8S3122X16 datasheet(6/44 Pages) SAMSUNG

Part #	S8S3122X16

Description	256K x 16 SDRAM

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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S8S3122X16

CMOS SDRAM

Ver 0.0 Sep. '01

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

VIN, VOUT

-1.0 ~ 4.6

V

Voltage on VDD supply relative to Vss

VDD, VDDQ

-1.0 ~ 4.6

V

Storage temperature

TSTG

-55 ~ +150

°C

Power dissipation

PD

1

W

Short circuit current

IOS

50

mA

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70

°C)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

VDD, VDDQ

3.0

3.3

3.6

V

Input logic high votlage

VIH

2.0

3.0

VDDQ+0.3

V

1

Input logic low voltage

VIL

-0.3

0

0.8

V

2

Output logic high voltage

VOH

2.4

-

V

IOH = -2mA

Output logic low voltage

VOL

-

0.4

V

IOL = 2mA

Input leakage current

ILI

-10

-

10

uA

3

Note :

CAPACITANCE (VDD = 3.3V, TA = 23

°C, f = 1MHz, VREF =1.4V ± 200 mV)

Symbol

Min

Max

Unit

Clock

CCLK

2

4

pF

RAS, CAS, WE, CS, CKE, L(U)DQM

CIN

2

4

pF

Address

CADD

2

4

pF

DQ0 ~ DQ15

COUT

3

5

pF

1. VIH (max) = 5.6V AC. The overshoot voltage duration is

≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is

≤ 3ns.

3. Any input 0V

≤ VIN ≤ VDDQ.

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

:

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

Value

Unit

Decoupling Capacitance between VDD and VSS

CDC1

0.1 + 0.01

uF

Decoupling Capacitance between VDDQ and VSSQ

CDC2

0.1 + 0.01

uF

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

Note :

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