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TCAN1051V-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
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TCAN1051V-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 38 page 11 TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1 TCAN1051HV-Q1, TCAN1051G-Q1, TCAN1051GV-Q1 TCAN1051HG-Q1, TCAN1051HGV-Q1 www.ti.com SLLSET0C – OCTOBER 2016 – REVISED MAY 2017 Product Folder Links: TCAN1051-Q1 TCAN1051V-Q1 TCAN1051H-Q1 TCAN1051HV-Q1 TCAN1051G-Q1 TCAN1051GV-Q1 TCAN1051HG-Q1 TCAN1051HGV-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated (1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V, RL = 60 Ω. 7.7 Switching Characteristics Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT DEVICE SWITCHING CHARACTERISTICS tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant See Figure 8, S = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 100 160 ns tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive 110 175 tMODE Mode change time, from Normal to Silent or from Silent to Normal See Figure 7 1 10 µs DRIVER SWITCHING CHARACTERISTICS tpHR Propagation delay time, high TXD to driver recessive (dominant to recessive) See Figure 5, S = 0 V, RL = 60 Ω, CL = 100 pF, RCM = open 75 ns tpLD Propagation delay time, low TXD to driver dominant (recessive to dominant) 55 tsk(p) Pulse skew (|tpHR - tpLD|) 20 tR Differential output signal rise time 45 tF Differential output signal fall time 45 tTXD_DTO Dominant timeout See Figure 10, S = 0 V, RL = 60 Ω, CL = open 1.2 3.8 ms RECEIVER SWITCHING CHARACTERISTICS tpRH Propagation delay time, bus recessive input to high output (Dominant to Recessive) See Figure 6, S = 0 V, CL(RXD) = 15 pF 65 ns tpDL Propagation delay time, bus dominant input to low output (Recessive to Dominant) 50 ns tR RXD Output signal rise time 10 ns tF RXD Output signal fall time 10 ns FD Timing Parameters tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns, all devices See Figure 9 , S = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF, ΔtREC = tBIT(RXD) - tBIT(BUS) 435 530 ns Bit time on CAN bus output pins with tBIT(TXD) = 200 ns, G device variants only 155 210 tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns, all devices 400 550 Bit time on RXD output pins with tBIT(TXD) = 200 ns, G device variants only 120 220 ΔtREC Receiver timing symmetry with tBIT(TXD) = 500 ns, all devices -65 40 Receiver timing symmetry with tBIT(TXD) = 200 ns, G device variants only -45 15 |
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