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ALD310702PCL Datasheet(PDF) 2 Page - Advanced Linear Devices |
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ALD310702PCL Datasheet(HTML) 2 Page - Advanced Linear Devices |
2 / 9 page ALD310702A/ALD310702, Vers. 1.1 Advanced Linear Devices, Inc. 2 of 9 These devices are built to offer minimum offset voltage and differential thermal response, and they can also be used for switching and amplifying applications in -0.40V to -8.0V (+/-0.20V to +/-4.0V) powered systems where low input bias current, low input capacitance, and fast switching speed are desired. These devices, exhibiting well controlled turn-off and sub-threshold characteristics, operate the same as standard enhancement mode P-Channel MOSFETs. However, the precision of the Gate Threshold Voltage enable two key additional characteristics, or operating features. First, the operating current level varies exponentially with gate bias voltage at GENERAL DESCRIPTION (cont.) or below the Gate Threshold Voltage (subthreshold region). Second, the circuit can be biased and operated in the subthreshold region with nA of bias current and nW of power dissipation. For most general applications, connect the V+ pin to the most positive voltage and the V- and IC (internally-connected) pins to the most negative voltage in the system. All other pins must have voltages within these voltage limits at all times. Standard ESD protection facilities and procedures for static sensitive devices are required when handling these devices. ABSOLUTE MAXIMUM RATINGS Drain-Source voltage, VDS -8.0V Gate-Source voltage, VGS -8.0V Operating Current 80mA Power dissipation 500mW Operating temperature range SCL, PCL 0°C to +70°C Storage temperature range -65°C to +150°C Lead temperature, 10 seconds +260°C CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. Notes: 1 Consists of junction leakage currents 2 Sample tested parameters OPERATING ELECTRICAL CHARACTERISTICS V+ = +5V V- = GND TA = 25°C unless otherwise specified ALD310702A ALD310702 Gate Threshold VGS(th) -0.22 -0.20 -0.18 -0.22 -0.20 -0.18 V IDS = -1µA, VDS = -0.1V Voltage Offset Voltage VOS 1 2 2 10 mV VGS(th)M1 - VGS(th)M2 or VGS(th)M3 - VGS(th)M4 Gate Threshold TCVGS(th) -2 -2 mV/°C Temperature Drain Source On IDS(ON) -2.03 -2.03 mA VGS = VDS = -5.0V Current Transconductance GFS 570 570 µA/V VGS = VDS = -5.0V Current2 Transconductance ∆GFS 11 % VGS = VDS = -5.0V Mismatch Output Conductance2 GOS 48 48 µA/V VGS(th) = -4.0V, VDS = -5.0V Drain Source On RDS(ON) 1.14 1.14 KΩ VGS = -5.0V, Resistance VDS = -0.1V Drain Source On ∆RDS(ON) 11 % Resistance Mismatch Drain Source BVDSX -8.0 -8.0 V Breakdown Drain Source IDS (OFF) 400 400 pA Leakage Current1 Gate Leakage Current IGSS 200 200 pA Input Capacitance 2 CISS 2.5 2.5 pF Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions |
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