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BQ294522DRVT Datasheet(PDF) 4 Page - Texas Instruments |
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BQ294522DRVT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 26 page 1 2 3 4 5 6 OUT VDD V1 V3 V2 VSS PWR PAD 4 bq294502, bq294504, bq294512, bq294514 bq294515, bq294522, bq294524, bq294532 bq294533, bq294562, bq294572, bq294582, bq294592 SLUSAJ3F – SEPTEMBER 2011 – REVISED JUNE 2017 www.ti.com Product Folder Links: bq294502 bq294504 bq294512 bq294514 bq294515 bq294522 bq294524 bq294532 bq294533 bq294562 bq294572 bq294582 bq294592 Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated (1) Product Preview only 5 Device Options TA PART NUMBER OVP (V) DELAY TIME (s) –40°C to +110°C bq294502 4.35 4 bq294504 4.35 6.5 bq294512 4.4 4 bq294514 4.4 6.5 bq294515 4.425 4 bq294522 4.45 4 bq294524 4.45 6.5 bq294532 4.5 4 bq294533 4.5 6.5 bq294562 4.25 4 bq294572 4 4 bq294582 4.225 4 bq294584(1) 4.225 6.5 bq294592 4.3 4 6 Pin Configuration and Functions DRV Package 6-Pin SON Top View Pin Functions PIN I/O DESCRIPTION NAME NO. OUT 6 OA Output drive for external N-channel FET. PWRPAD — — VSS pin to be connected to the PWRPAD on the printed-circuit-board (PCB) for proper operation. V1 4 IA Sense input for positive voltage of the lowest cell in the stack. V2 2 IA Sense input for positive voltage of the second cell from the bottom of the stack. V3 1 IA Sense input for positive voltage of the third cell from the bottom of the stack. VDD 5 P Power supply VSS 3 P Electrically connected to IC ground and negative terminal of the lowest cell in the stack. |
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